🚀 go-pugleaf

Does any one understand the lock-step / interleave mode on the i840
chipsets. I have read many of the Intel datasheets and more, but I am still
having a little trouble deciding if I can get more performance out of my
system by populating all of the DIMM rows.

Important system specs:
Supermicro PIIIDME motherboard / i840 based
dual PIII 600B
256MB PC-133 SDRAM / bank population as follows / 0:128MB - 1:128MB -
2:empty - 3:empty

When SDRAM configurations are used instead of RDRAM, the ram bus is only
driven at 100MHz, so I want to get most bandwidth out of the board. Because
of the 840 design, I must install ram in pairs (as 0 & 1 above). Will using
only 2 DIMMs give me the full 3.2GB/s burst available on 840 boards, or must
I populate all four banks for lock-step and interleaving to work. Also, it
seems that all four DIMMS may have to be the same for interleaving. Correct?

I have done my research and have quite a deep background and a good
understanding of what is going on, but I am a bit confused and the below
data from Supermicro is contradictory (as is other data I have.) Therefore,
I would appreciate any clarification. I have included some info from Intel's
website for anyone interested in reading. Yeah I know, this is a long post,
but this has been bugging me for months.


From the Supermicro website.
http://www.supermicro.com/PRODUCT/MotherBoards/840/PIIIDME.htm
Some of the specs of the Supermicro PIIIDME:
Intel's 840 "Carmel" Chipset
(82840 MCH + 82801AA ICH + 2 x 82804AA MRH-S + 82806AA P64H)
- Up to 4 GB PC100 compatible SDRAM
- Memory operates in interleave mode for increased performance

There seems to be only two MRH-S units on this board, so how can it operate
in interleave and be in compliance with the Intel datasheet notes below. It
seems there should be four MRH-S repeaters for interleave mode. Any
utilities that can check/bench memory bandwidth. I have SiSoft Millenium,
but it crashes on the memory test under Win2K.

The main thing that I want to know is if I should bother populating all four
DIMM slots.




Here is what the Intel MCH Datasheet says.
http://channel.intel.com/design/chipsets/datashts/298020.htm
_______
The 82840 MCH uses the 82804AA Memory Repeater Hub for SDRAM (MRH-S) to
provide the support
for SDRAM devices. The 82840 MCH supports MRH-Ss operating in lock-step on
its dual Rambus*
channels which results in a 1.6 GB/s burst bandwidth for non-interleave mode
operation and 3.2 GB/s
burst bandwidth for interleave mode operation. The MCH supports a total of 8
SDRAM Row-Pairs. Each SDRAM Row-Pair consists of a row accessed via the MCH
Direct Rambus* interface A and a row accessed via the MCH Rambus* interface
B. MRH-S_0 contains physical Row-Pairs 0-3. MRH-S_1 contains physical
Row-Pairs 4-7. SDRAM DIMM are always populated in Row-Pairs.
The MCH supports two MRH-S configurations:

Non-Interleave Address Mode. Non-interleave address mode can be used when
the number of SDRAM
Row-Pair is even in the memory array, and it is required when the number of
Row-Pair is odd. Each Direct
Rambus* interface is populated with one or two MRH-Ss. A MRH-S pair consists
of a MRH-S on the
Direct Rambus* interface A and another MRH-S on the Direct Rambus* interface
B for lock-step
operation. SDRAM is always populated in Row-Pairs with the same device
technology.

*** The chipset always operates in lock-step mode regardless of the number
of MRH-S units. *** Correct? ***

Interleave Address Mode. Interleave address mode requires exactly 2 MRH-Ss
per Direct Rambus*
interface for a total of 4 MRH-Ss in the memory array. SDRAM is always
populated in Row-Pair Sets with
the same device technology in interleave address mode. A "Row-Pair Set"
consists of one Row-Pair on
the first MRH-S pair and another Row-Pair on the second MRH-S pair.

*** This means four DIMMS are accessed simultaneously in lock-step /
interleave mode. *** Correct? ***

A MRH-S pair consists of a MRH-S on the Direct Rambus* interface A and
another MRH-S on the Direct Rambus* interface B for lock-step operation. The
number of SDRAM Row-Pairs is always even for interleave mode. MRH-S_0
contains physical Row-Pairs 0-3. MRH-S_1 contains physical Row-Pairs 4-7.
The Row-Pair Sets become 0/4, 1/5, 2/6, 3/7. Memory must be populated as
full Row-Pair Sets in interleaved mode. Thus, for example, Row-Pair 0 in
MRH-S_0 becomes a Set with Row-Pair 4 in MRH-S_1.
_______