🚀 go-pugleaf

Our group is building a computer peripheral and We are using a PPC coupled
with a MPC106 PCI bridge. Is there a lurking expert that could clarify a
few points for me:

1. I assume the added value of a "PCI bridge" is to have a bunch of
processors & peripherals with proprietary bus architectures talk to each
other, is that right?

2. The bridge has some signals spec'ed as inputs & outputs. Is it either
one or the other or do some signals switch from inputs to outputs
dynamically in a typical operation? I am referring to signals like "frame"
or "command/byte enable" ( I think the bridge can be used as PCI master or
PCI target, and those signals depend on which one but would like to
confirm)

3. What is the sequence for a peripheral access. Does it look like this:
   - Processor initiates transaction on proprietary bus
   - Bridge translates the transaction to the target peripheral while
__processor stalls__.
   - Bridge at the peripheral input translates the transaction on
peripheral proprietary bus
   - Peripheral responds, and data flows through the PCI bus through the
bridge to the processor
   - And the processor finally gets the data.

4. Is it possible to have a 8 kb burst of data going throught the PCI bus?
Something like specify address once, then increment 8000 times. Is that
supported? If yes, can it be interrupted? If yes, how would that happen?
This is my main question. I have to find out for Monday :)

5. Any pointer to a FAQ, PCI bridges for dummies or the like would be very
appreciated.


Thanks for your help

Guillaume Comeau