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Article #2

LOOKING FOR A CHIP/LAYOUT VERIFICATION ENGINEER!

#2
From: Grace Law
Date: Wed, 26 Mar 1997 00:00
37 lines
2302 bytes
Company:	Software Engineering Solutions, Inc.
Position:	Chip/Layout Verification Engineer
Date Posted:	3/26/97

You asked for it!  A job as a Chip/Layout Verification Engineer
in one of the hottest companies in the Silicon Valley.
You will be doing Chip layout verification for Fiber Channel
interface ASIC.

DUTIES:		Extraction of LSI test vectors
		Support for netlist changes during layout 
		 arising from logic or timing defects found
		Post-layout timing verification


SKILLS:		Verilog (required)
		Simulation test coding, gate level (required)
		Test vector extraction (required)
		LSI experience (strongly preferred)
		LSI Toolkit (strongly preferred)
		MOTIVE timing verification (preferred)

Location:	Cupertino
When:		ASAP!
Salary:		$60-$94/hr.
Duration:	3+ months

Call or send resumes to:

Naomi Tran
Software Engineering Solutions, Inc.
914 N. Rengstorff Ave.
Mountain View, CA 94042
Voice:	415-969-0141
Fax:	415-969-0177
Email:	tran@sesinc.com  (text only)
Technical Details
Message-ID: <3339E1F6.22A3@ricochet.net>
Path: arc1-ca.pugleaf.net!unknown!not-for-mail

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From: Grace Law <sesinc@ricochet.net>
Subject: LOOKING FOR A CHIP/LAYOUT VERIFICATION ENGINEER!
Date: 1997/03/26
Message-ID: <3339E1F6.22A3@ricochet.net>
X-Deja-AN: 228641405
Organization: Software Engineering Solutions, Inc
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