🚀 go-pugleaf

In article <1992Dec15.205835.643@zooid.guild.org> Mark Kovarski <kovarski@zooid.guild.org> writes:
>mov al,74
>out 43,al

port 0x43 in this 8253 timer control port
0x74 = 01110100b which means 01 = select timer 1, DRAM refresh
                             11 = Program timer w/ LSB followed by MSB
                             0100 = Triggered strobe (software), whatever
                                    that means.

In other words, it's programming a new refresh rate for your DRAM.
The lower the frequency, the faster your computer runs (because it's 
not being interrupted so often to refresh your DRAM).  However, 
DRAM's have a limit, and each DRAM is different.  If the refresh 
frequency drops to a value that's too low, then some of your DRAM
chips will lose their contents, and a parity error will result.

The whole idea behind this is that the default value (15 microseconds,
I think) is way too conservative, and that most modern chips can handle
a much slower setting.

>mov al,ff
>out 41,al
>mov al,ff
>out 41,al

This programs the counter with 0xFFFF, which is the maximum (i.e.
slowest setting).  There is no way that your DRAM can handle this,
so it's no wonder it causes a parity error.  The second byte is
the MSB, so if you want to try a value of 0x1000, then you need:

>mov al,0
>out 41,al
>mov al,10
>out 41,al

Try different values, and see how if your computer generates parity
errors.  OS/2 will trap this, so it won't work.  Maybe I'll get around
to writing an OS/2 device driver for this, when I have some free time.