Article View: alt.lang.asm
Article #157Re: DRAM refresh rates
From: Jerzy Tarasiuk
Date: Tue, 12 Jan 1993 19:43
Date: Tue, 12 Jan 1993 19:43
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2693 bytes
>>>>> On 30 Dec 1992 18:03:29 GMT, chbl@sbustd.rz.uni-sb.de (Christian Blum) said: CB> NNTP-Posting-Host: sbustd.stud.uni-sb.de CB> rnichols@cbnewsg.cb.att.com (robert.k.nichols) writes: > In article <1992Dec27.105039.25690@microsoft.com> chuckst@microsoft.com (Chuck Strouss) writes: > ... > The length of time that a DRAM cell can hold its content without > refresh is inversely proportional to the leakage current in the > device. The leakage current, in turn, is an *exponential* function of > temperature. What this boils down to is that a device with cells that > must be refreshed every 2 ms at max rated temperature will hold > information for over 20 SECONDS at a junction temperature of 25 C. > One particularly nasty consequence of this is that it becomes very > difficult to tell whether refresh is working correctly in your system, > and even harder to devise a test which will reliably detect memory > cells that might be marginal (from a refresh standpoint) at high > temperatures. CB> Correct, but it was a simple question and I wanted to give a simple CB> answer. I know that DRAMs can do it without refresh for seconds at CB> room temperature, but it's really not advisable for a greenhorn to CB> try it... CB> BTW, I wrote a program that switches to lower refresh rates whenever CB> possible (some PCs fail to access diskettes if the rate has been CB> changed, and the beep won't work correctly). If anyone is interested CB> in it, please email. It is possible to write a program testing DRAM refresh assuming we have some memory which will not be destroyed when refresh discontinues to work. I suppose video RAM can be used for this purpose. Need: disable non-maskable interrupt and disable (CLI) interrupts, put program (code, data, stack) in the RAM, put some pattern data in memory, reduce refresh rate, wait some time (normal refresh in PC is 17us/address, suppose 4ms to go through all addresses, can wait e.g. 55 ms), then check the data and NMI signal (memory parity error gives NMI). Repeat it for several patterns. Before the test: do large memory moves on tested cells to 'heat' them.
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Newsgroups: alt.lang.asm,comp.sys.ibm.pc.hardware Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!sunic!fuw.edu.pl!cocos!jt From: jt@fuw.edu.pl (Jerzy Tarasiuk) Subject: Re: DRAM refresh rates In-Reply-To: chbl@sbustd.rz.uni-sb.de's message of 30 Dec 1992 18:03:29 GMT Message-ID: <JT.93Jan12204346@fizyk1.fuw.edu.pl> Sender: news@fuw.edu.pl Nntp-Posting-Host: fizyk1 Organization: Warsaw University Physics Dept. References: <1992Dec29.012957.14287@cbfsb.cb.att.com> <1hso9hINNeks@sbusol.rz.uni-sb.de> Date: Tue, 12 Jan 1993 19:43:46 GMT Lines: 35