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>Question everyone.  We all know that:
>
>	mov	al,20h
>	out	20h,al
>
>tells the processor to process the other interrupts.
>
>What do other ALs do?  I'm interested in three in particular, when AL = 11h,
>12h, and 13h.

  You need to get the data sheet for the Intel 8259A interrupt controller.
Port 20h is connected directly to this chip, and that data sheet is the
only place where I've seen decent doc on what all the functions are.

                                                  -Kevin

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>   You need to get the data sheet for the Intel 8259A interrupt controller.
> Port 20h is connected directly to this chip, and that data sheet is the
> only place where I've seen decent doc on what all the functions are.

Any ideas on where to obtain a data sheet?  Perhaps someone could look in their
Intel manuals (which I don't have).

-Josh

In article <1992Oct27.133937.60159@cc.usu.edu> sl8nl@cc.usu.edu writes:
> Question everyone.  We all know that:
>
>	   mov	al,20h
>	   out	20h,al
>
>  tells the processor to process the other interrupts.
>
>  What do other ALs do?  I'm interested in three in particular, when AL = 11h,
>  12h, and 13h.
>
>  Thanks!
>
>  Joshua Jensen

Values of 11h, 12h and 13h, when written to port 20h, signify the
start of an initialization sequence.  This is called ICW1
(Initialization Command Word 1), and is triggered by A0 == 0 (ie port
20, not port 21) and bit 4==1 in the byte written there.  ICW1 is
followed by a write of ICW2, and then possibly ICW3 (in a master/slave
PIC system; ie AT, not PC) and then followed by ICW4 if the
appropriate bit in ICW1 was set to indicate that you would be writing
an ICW4.  Make sense :-) Here's the picture of ICW1:

	b7   b6   b5    b4    b3   b2   b1   b0
        |__________|     1     |    |    |    |____ 1 = ICW4 needed
             |                 |    |    |_________ 1 = single, 0 = cascaded
          A7-A5 of             |    |______________ Call address interval
         Interrupt             |                      1 = 4 byte interval
       Vector  Address         |                      0 = 8 byte interval
       (MCS 80/85 mode)        |___________________ 1 = level triggered mode
                                                    0 = edge triggered mode


In your examples, 11h means no ICW4, cascaded mode, edge triggered
mode (The call address interval and interrupt vector address are
ignored in iAPx-88/86 mode). 12h means no ICW4 and single mode, edge
triggered.  13h means ICW4 needed, single mode and edge triggered.

to complete the picture, ICW2 is used to help generate vectoring
addresses (on MCS-80/85 systems) and vector bytes (on iAPX-88/86).

ICW3 is only present in cascaded systems, and is used to tell the
master which interrupt request line is a cascade input, and to tell
the slave its "slave id".  During an interrupt cycle, the master will
enable an interrupting slave to present it data onto the data bus at
correct times during the cycle.

ICW4 is used to control additional features of the 8259.  One of these is
the operational mode.  bit 0 in ICW4 controls whether the unit operates
in MCS-80/85 mode or iAPX-88/86 mode.  If b0 = 0 (the default if no ICW4
is sent) then the unit is set to MCS-80/85 mode.  This is not what you
want on a PC, so you should almost always see an ICW4.

BTW, the 20h in al in "out 20h,al" is the EOI (for End Of Interrupt),
and in a master/slave configuration (cascaded; ie PC-AT), you are
required to EOI both the master and the slave.  on the PC-AT and
clones, the slave PIC is at port A0h. The EOI is called an Operation
Control Word, or OCW.

Brian.
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> In your examples, 11h means no ICW4, cascaded mode, edge triggered
> mode (The call address interval and interrupt vector address are
> ignored in iAPx-88/86 mode). 12h means no ICW4 and single mode, edge
> triggered.  13h means ICW4 needed, single mode and edge triggered.
> 
> to complete the picture, ICW2 is used to help generate vectoring
> addresses (on MCS-80/85 systems) and vector bytes (on iAPX-88/86).

OK, Brian, thanks for the response.  Now, off the top of my head, here is the
code.  Bear in mind taht this is from some communication routines that I have.
This is one section of the code (from what I can remember off the top of my
head).  I'd ask the original programmer, but there is no address.

		mov	al,11h
		out	20h,al

		mov	al,8
		out	21h,al

		mov	al,4
		out	21h,al

		mov	al,3
		out	21h,al

		mov	al,20h
		out	20h,al

Note that this code was in the interrupt set code, after the cli, but before
the sti (which was just after the final line above).

What exactly does this do?  The interrupt won't run without it (although it
should).  The actual interrupt also doesn't use a mov al,20h; out 20h,al at the
end of the interrupt.

I(deas?

Joshua Jensen

>>>>> On 2 Nov 92 14:14:03 MDT, sl8nl@cc.usu.edu said:
> code.  Bear in mind taht this is from some communication routines that I have.
> This is one section of the code (from what I can remember off the top of my
> head).  I'd ask the original programmer, but there is no address.
(I have rewritten the code in more compact form to save net bandwidth):
	outp(0x20,0x11);	/* ICW1: cascade, edge triggered, normal */
	outp(0x21,0x08);	/* ICW2: base int=8, normally */
	outp(0x21,0x04);	/* ICW3: slave at IRQ2, normal on AT */
	outp(0x21,0x03);	/* ICW4: auto EOI - no need for out 20,20
				 *	 non-buffered mode
				 *	 no special fully-nested mode */
	outp(0x20,0x20);	/* OCW: End-Of-Interrupt */
> What exactly does this do?  The interrupt won't run without it (although it
> should).  The actual interrupt also doesn't use a mov al,20h; out 20h,al at the
> end of the interrupt.

It is almost same as AT or 386 computer BIOS does on initialization
of 8259 (I looked BIOS code on two computers here), with one exception:
the auto-EOI which is not set by BIOS (XT 8259 programming is *MUCH*
different since XT has only one 8259, MUST NOT program cascade mode).
The auto-EOI means no need for out 20h,20h on every interrupt.