🚀 go-pugleaf

From article <HOLMER.92Dec18174207@rose.eecs.nwu.edu>, by holmer@eecs.nwu.edu (Bruce Holmer):
> 
> Does someone have a table of instruction cycle
> counts for a high-end PDP-8?  I'd need to know
> about how many cycles the different addressing
> modes require and how to calculate the cycle
> count for the OPR instructions.

There were two different memory cycle times on the PDP-8/E (that was probably
the highest of the high-end PDP-8 machines):  1200ns and 1400ns.

An instruction fetch was one short cycle.
Indirect addressing cost one short cycle, unless it was through an
  autoindex register, in which case you pay for a long cycle.
Operand fetch for AND and TAD cost one long cycle.
Operand fetch/increment/store for ISZ cost one long cycle.
Operand store for DCA and JMS cost one long cycle.
JMP cost nothing other than the instruction fetch and indirect cycles.
IOT to omnibus peripherals cost nothing beyond the instruction fetch cycle.
OPR for non EAE instructions cost nothing beyond the instruction fetch cycle.

These figures are for the standard PDP-8 memory, and must be adjusted if
you want to talk about the various strange things that happened when they
abandoned core, particularly, it should be noted that the ROM technology
of the mid 1970's was a bit on the slow side.

				Doug Jones
				jones@cs.uiowa.edu