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Article #242Re: Dual processors ?
From: Lee Sau Dan
Date: Fri, 10 Jan 2003 08:09
Date: Fri, 10 Jan 2003 08:09
56 lines
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3522 bytes
>>>>> "Christopher" == Christopher Browne <cbbrowne@acm.org> writes:
Christopher> On the other hand, the two CPUs have to share:
Christopher> a) The same memory bus;
This is only a concern when there is a cache MISS!
Christopher> b) The same memory caches;
Wrong, somehow. Each CPU has its own L1 cache.
Christopher> c) The same I/O buses.
True. And in this case, the OS schedules the things nicely, as in a
single CPU system. E.g. disk read requests from any CPU would be put
on the same queue, and then served by the disk scheduler (which
optimizes the performance with the elevator algorithm). It only
matters when you generate 2x the amount of I/O operations.
Christopher> If the CPUs are working on totally different sorts of
Christopher> things, b) can lead in particular to "sucky
Christopher> performance."
You're wrong. They each has its own L1 cache. And accessing
different sorts of things is actually good in this case: if they were
accessing the same things, they MUST invalidate the L1 cache of each
other often, defeating the purpose of the cache. If they're accessing
different things, they each keep those things in their own L1 cache
happily. And this generates much less cache-invalidation or refetch.
Christopher> If both CPUs are /reading/ the same code, or
Christopher> /reading/ the same memory locations, there could
Christopher> conceivably be a big /WIN/ as a result;
Obviously not. They have to invalidate the L1 cache of each other
often, making the L1 cache almost useless.
Christopher> the first CPU already read the data, so it's in cache
Christopher> so that the second CPU doesn't have to read it in.
Only true for the external cache (L2 or higher). And usually, there
is just plentify L2 cache to handle the needs of both CPUs. If not,
blame the motherboard designers.
--
Lee Sau Dan ���u��(Big5) ~{@nJX6X~}(HZ)
E-mail: danlee@informatik.uni-freiburg.de
Home page: http://www.informatik.uni-freiburg.de/~danlee
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X-Google-Language: ENGLISH,ASCII X-Google-Thread: 114381,acfea8e5e9ff6f15 X-Google-Attributes: gid114381,public X-Google-Thread: 102b32,acfea8e5e9ff6f15 X-Google-Attributes: gid102b32,public X-Google-Thread: 102983,acfea8e5e9ff6f15 X-Google-Attributes: gid102983,public X-Google-ArrivalTime: 2003-01-10 01:45:03 PST Path: arc1-ca.pugleaf.net!archiver1.google.com!news1.google.com!newsfeed.stanford.edu!news.uchicago.edu!yellow.newsread.com!netaxs.com!newsread.com!newsfeed.stueberl.de!feed.news.nacamar.de!news.belwue.de!news.uni-freiburg.de!not-for-mail From: Lee Sau Dan <danlee@informatik.uni-freiburg.de> Newsgroups: aus.computers.linux,comp.os.linux.hardware,aus.ads.forsale.computers.used Subject: Re: Dual processors ? Date: 10 Jan 2003 09:09:55 +0100 Organization: Rechenzentrum der Universitaet Freiburg, Germany Lines: 56 Message-ID: <m3vg0ygf4k.fsf@mika.informatik.uni-freiburg.de> References: <pan.2003.01.03.13.58.10.249319@iprimus.com.au> <av578p$c8s17$1@ID-99293.news.dfncis.de> <av5qtf$tcf$1@lust.ihug.co.nz> <fbf82913.0301040421.1a35bdfa@posting.google.com> <3E178C63.7040901@netscape.net> <av8a3u$d2h2f$1@ID-125932.news.dfncis.de> NNTP-Posting-Host: camaro.informatik.uni-freiburg.de Mime-Version: 1.0 Content-Type: text/plain; charset=cn-big5 Content-Transfer-Encoding: 8bit User-Agent: Gnus/5.0808 (Gnus v5.8.8) Emacs/20.7