🚀 go-pugleaf

Dear Colleagues,

You are cordially invited to the following distinguashed lecture series
to be given at our PARALLEL AND DISTRIBUTED COMPUTING WEEK organized by
School of Computing and Information Technology at Griffith University,
14-16 December 1998.

Attendence to the lectures is free of charge. All are welcome!

--Hong



           *******************************************
           *                                         *
           * PARALLEL AND DISTRIBUTED COMPUTING WEEK *
           *                                         *
           *          14-16 December 1998            *
           *                                         *     
           *******************************************


          School of Computing and Information Technology
         Griffith University, Nathan, QLD 4111, Australia

             Tel: 07-38755002       Fax: 07-38755051 
                       hong@cit.gu.edu.au


                            PROGRAM
                            =======


Monday 14 December
******************
Venue: SCI 2 Room 0.04, Nathan Campus, Griffith University

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9:30 - 10:30 am
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Parallel Processing: Past, Present, and Future

Jie Wu
Florida Atlantic University

ABSTRACT:

Parallel computing is one of the most exciting technologies to achieve
prominence since the invention of electronic computers.
But the departures from the Von Neumann computational model create
many questions and problems. What kind of applications have sufficient
parallelism? What will be the nature of the processing elements, and
how will they communicate with each other? What will the new computational
model be? What will the software be like? This talk focuses on the total
design problem involved in parallel processing. A brief history of parallel
computing is presented first, followed by a list of major issues in the
design of a parallel system. Three major design approaches are discussed:
control (task) parallelism, data parallelism, and pipelining. Finally,
we provide our own view of the future of parallel processing.

SHORT BIO ABOUT THE SPEAKER:

Jie Wu received the B.S. degree in computer engineering in 1982 and
the M.S. degree in computer science in 1985, from Shanghai University
of Science and Technology, and the Ph.D. degree in computer engineering
from Florida Atlantic University, Boca Raton, Florida, in 1989. Between
1985-1987, he taught at Shanghai University of Science and Technology.
Since August 1989 he has been with the Department of Computer Science
and Engineering, Florida Atlantic University where he is a Professor
and the Director of CSE graduate programs. Dr. Wu has published over
100 papers in various journal and conference proceedings such as IEEE
Transactions on Software Engineering, IEEE Transactions on Computers,
IEEE Transactions on Parallel and Distributed Systems, Journal of
Parallel and Distributed Computing, and Concurrency: Practice and
Experience. His research interests are in the area of parallel/
distributed systems, fault-tolerant computing, interconnection
networks, Petri net applications, and software engineering.
   Dr. Wu serves on the editorial board of the International Journal on
Computers and Applications.  He served on the program committees for
the 1996 and 1998 IEEE International Conference on Distributed Computing
Systems. He will be the program co-chair of the 12th ISCA International
Conference on Parallel and Distributed Computing Systems in 1999
and the local arrangements chair of the 5th IEEE International Symposium
on High-Performance Computer Architecture in 1999. Dr. Wu is also
a co-guest-editor of a special issue in IEEE Transactions on Parallel
and Distributed Systems on  "Challenges in Designing Fault-Tolerant
Routing in Networks". He is the author of the text "Distributed System
Design" published by the CRC press.  Dr. Wu a recipient of the 1996-97
Researcher of the Year Award at Florida Atlantic University.
He is an IEEE Computer Society Distinguished Visitor. Dr. Wu is a
member of Upsilon Pi Epsilon and ACM, and a senior member of IEEE.


---------------
10:30 - 11:00 am
----------------

Morning tea

----------------
11:00 - 12:00 am
----------------

Optimal parallel prefix circuits with fan-out at most 4

Yen-Chun Lin
National Taiwan University of Science and Technology 

ABSTRACT:

Given n values x1, x2, ... , xn and an associative binary
operation, denoted by o, the prefix problem is to compute x1 o x2 o ...
o xi, 1 <= i <= n.  Many combinational circuits for solving the prefix
problem, called prefix circuits, have been designed.  Because the size
s(D(n)) and the depth d(D(n)) of an n-input prefix circuit D(n) satisfy
the inequality d(D(n)) + s(D(n)) >= 2n -  2, a prefix circuit is
depth-size optimal if d(D(n)) + s(D(n)) = 2n -  2.  In general, a prefix
circuit with smaller depth is faster than one with greater depth,
especially when most nodes have the same fan-out.  A node with greater
fan-out occupies more chip area and is slower in VLSI implementation. 
In this paper, we construct a depth-size optimal prefix circuit F4(n),
with fan-out at most 4 and depth 2 lg n - 3, 2 lg n -  4, or 2 lg n - 5,
depending on the value of n.  The depth of F4(n) is smaller than that of
any other prefix circuit except two prefix circuits denoted by LYD(n)
and SL(n).  Although d(LYD(n)) + 2 >= d(F4(n)) >= d(LYD(n)), LYD(n) has a
drawback of greater fan-out around 2 lg n - 2.  SL(n) has the same depth
and size as F4(n), but SL(n) also has greater fan-out around lg n + 1. 
Thus, F4(n) may be faster than all other prefix circuits and needs less 
VLSI area than all other depth-size optimal parallel prefix circuits
with fan-out greater than 4.

SHORT BIO ABOUT THE SPEAKER:

Yen-Chun Lin received his Ph.D. degree in electrical engineering from
National Taiwan University.  Since 1988 he has been on the faculty at
National Taiwan Institute of Technology, which was renamed as National
Taiwan University of Science and Technology in 1997.  He has been a
Professor in the Department of Electronic Engineering since 1993.  He
was a Visiting Scientist at the IBM Almaden Research Center, San Jose,
CA, from 1993 to 1994.  His research interests include parallel
algorithms and architectures.

---------------
12:00 - 1:30 pm
---------------

Lunch break

---------------
1:30 - 2:30 pm
---------------
Venue: 

Language Constructs and Run-time System 
for Parallel Cellular Programming

Domenico Talia
ISI-CNR, Italy

ABATRACT:

This talk presents the main features of CARPET, a high-level programming 
language based on cellular automata theory. The language has been designed 
for supporting the development of parallel high-performance software 
abstracting from the parallel architecture on which programs run. A CARPET 
user can write cellular programs to describe the actions of a very large 
number of simple active agents interacting locally. The CARPET run-time 
system allows a user to observe, also in a graphical format, the global
results that arise from their parallel execution.

SHORT BIO ABOUT THE SPEAKER:

Domenico Talia he is a senior researcher at the ISI-CNR - Institute of
Systems Analysis and Information Technology of the Italian National
Research Council and a lecturer at the University of Calabria. Talia
received the Laurea degree in Physics at University of Calabria and he has
been a researcher at CRAI (Consortium for Research and Applications of
Informatics). His main research interests are on parallel computation,
concurrent programming languages, cellular automata, and parallel data
mining. Talia is a member of the Editorial Board of the IEEE Computer
Society Press, a member of the Editorial Board of the Parallel and
Distributed Practices journal, a member of the Advisory Board of Euro-Par,
and a Distinguished Speaker in the IEEE Computer Society Distinguished
Visitors Program. He published two books and about 80 papers in
international journals and conference proceedings. He is member of the ACM
and the IEEE Computer Society.

--------------
2:30 - 3:00 pm
--------------

Afternoon tea

--------------
3:00 - 4:00 pm
--------------

Parallel Relative Debugging - Finding errors in parallel programs

David Abramson
Monash University, Australia

ABSTRACT:

This talk will provide a brief introduction to relative debugging and how
it can be used to find errors in programs that have been ported to other
systems, or modified. The key to relative debugging is to use a working
version of the program to find erroneous regions. In 1995 a debugger called
Guard was produced, which tested some of the ideas on sequential programs.
Recent work has focused on supporting relative debugging for parallel
programs. We have incorporated support for data parallel programs written
in ZPL (from the University of Washington), and fixed decompositions of
data in MPI programs. The latter makes use of a novel transformation
algebra which allows the programmer to describe data transformations that
occur when the program is parallelised and the data decomposed. Current
development work also includes porting Guard to Windows/NT, which makes 
use of Microsoft's Active Debug Architecture.


SHORT BIO ABOUT THE SPEAKER:

Professor Abramson has been involved in computer architecture and high
performance computing research since 1979. Previous to joining Monash 
University in 1997, he has held appointments at Griffith University, CSIRO, 
and RMIT. At CSIRO he was the program leader of the Division of Information
Technology High Performance Computing Program, and was also an adjunct
Associate Professor at RMIT in Melbourne. He was also a program manager 
in the Co-operative Research Centre for Intelligent Decisions Systems. 
He is currently the head of the School of Computer Science and Software 
Engineering (CSSE) at Monash University, Australia. CSSE consists of 
over 65 academic staff members across 2 campuses. Abramson is currently 
project leader in the Co-operative Research Centre for Distributed 
Systems Nimrod Project. He is also Chief Investigator in several ARC 
funded research projects. 


Tuesday 15 December
*******************

---------------
9:00 - 10:00 am
---------------
Venue: Room Avro, Brisbane Parkroyal Hotel 

PDCN'98 Keynote Address (open to public):
Very High Performance Parametric Modelling on the Global Grid

David Abramson
Monash University, Australia

ABSTRACT:

This talk will discuss the design and implementation of a system which
allows users to pose very large parametric modelling experiments, and
execute these on a global meta-computer. The system, called Nimrod/G [1],
is based on a commercially available tool, Clustor [2] , and is implemented
on top of the Globus tool kit [3]. The talk will give some case studies of
how Clustor is used, followed by a discussion of scheduling issues on a
global meta computer using Globus. It will also address the design of high
performance decision support systems based on optimisation [4].


---------------
2:00 - 3:00 pm
---------------
Venue: SCI 2 Room 0.04, Nathan Campus, Griffith University

Network Performance of TESH: A New Hierarchical
Interconnection Network for 3-D Integration

Susumu Horiguchi
Japan Advanced Institute of Science and Technology, Japan

ABSTRACT:

Three dimensional (3D) stacked implementation has been proposed as a
new technology for massively parallel computers.  However, two major
limitations have hindered progress in this direction: the technology
for vertical interconnects and the high cost of such interconnects
in terms of silicon area. Each such vertical interconnect can use
significant area, on the order of $300 \mu m \times 300 \mu m$, thus
prohibiting their liberal use. Therefore, an interconnection philosophy
which minimizes these vertical links can contribute to the success of
a 3D implementation.  We have recently proposed such a network
called 'Tori Connected Meshes' (TESH). This network uses a very small
number of vertical links, compared to most other known networks.
This talk  addresses the architectural details of 3D stacked
implementation, and explores aspects such as the network diameter, the
peak number of vertical links, and VLSI layout area for the TESH
network as well as for several commonly used net7orks for parallel
computers.  It is shown that TESH possesses several attractive
features including small diameter, small number of wires -- in
particular small number of vertical links, and economical layout area.

SHORT BIO ABOUT THE SPEAKER:

Professor Susumu Horiguchi graduated from Department of
Communication Engineering, Tohoku University in 1976, and received the
MS. and Dr. degrees both from the same university in 1978 and 1981,
respectively.  He was a faculty of Department of Information Science
at Tohoku University from 1981 to 1992.  He was a visiting scientist
of IBM Thomas J. Watson Research Center from 1986 to 1987, a visiting
professor of The Center for Advanced Studies at the University of
Southwestern Louisiana in July-August 1994 and Department of Computer
Science, Texas A&M University in July-August 1997.
   He is currently a full Professor of the Graduate School of
Information Science at JAIST(Japan Advanced Institute of Science and
Technology) since 1992.  He has been`conducting his research group as
the chair of Multi-Media Integrated System Laboratory at JAIST.  He has
been involved in organizing many international workshops, symposia and
conference sponsored by IEEE, IEICE and IPS.  His research interest
has been mainly concerned with interconnection networks, parallel
computing algorithm, massively parallel processing, parallel computer
architecture, VLSI/WSI architecture, and Multi-Media Integral System.
   Dr.Horiguchi is a senior member of IEEE Computer Society,
and members of IEICE and IPS of Japan.


---------------
3:00 - 3:30 pm
---------------

Afternoon tea

---------------
3:30 - 4:30 pm
---------------
Venue: SCI 2 Room 0.04, Nathan Campus, Griffith University

Optimal Multi-stage Interconnection by Divide-and-Conquer Networks

Shuo-Yen Robert Li
The Chinese University of Hong Kong

ABSTRACT:

With a rigorous algebraic formulation of multi-stage interconnection
networks, we propose a measure for the layout complexity of an
inter-stage exchange based upon the traditional Manhattan model
of VLSI layout. The complexity of a 2^n x 2^n inter-stage exchange
turns out to be 2n-1. Meanwhile we establish a correspondence
between binary trees and multi-stage interconnection networks.
When an n-leave binary tree is as balanced as possible, its
associated network is called a 2^n x 2^n divide-and-conquer
network. Its layout complexity is then proved to be optimal 
among all 2^n x 2^n multi-stage interconnection networks.

SHORT BIO ABOUT THE SPEAKER:

Shuo-Yen Robert Li received the BS degree from National Taiwan
University in 1970 and the PhD degree from University of
California, Berkeley in 1974. Subsequently he taught applied 
mathematics at M.I.T. for two years and mathematics/statistics/CS
in University of Illinois at Chicago for three years. From 1979
to 1989, he was a technical member at Bell Labs and Bellcore
working on switching systems and principles of communication
and computation. Since 1989, he has been Professor of
Information Engineering at The Chinese University of Hong Kong.
Journal publications of Prof. Li have appeared in areas of
algorithms/complexity, communications, commutative algebra, 
computers, control, discrete mathematics, game theory, information 
theory, probability, statistics, and VLSI. He holds five
and half US patents. His work in 1982 on "Real-time Efficient 
STATPAC of No.1 TSPS" created US$49M savings for the Bell System.
In 1983 his management of the operator systems overload crisis 
settled a long-term dispute between Bell Labs and Southern Bell 
in a win-win.


Wednesay 16 December
********************

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9:00 - 10:00 am
---------------
Venue: Room Avro, Brisbane Parkroyal Hotel

PDCN'98 Keynote Address (open to public):
Fault-Tolerant Communication in Direct Networks

Jie Wu
Florida Atlantic University, USA

ABSTRAT:

One of the challenges in fault-tolerant communication is
to achieve certain objectives without excessive cost in
collecting and  maintaining fault information. We propose
an approach that achieves optimal routing with limited amount
of global fault information. This approach is illustrated
in regular and irregular networks. Among regular networks,
the concept of a safety level (vector) is introduced that 
can be applied to hypercube- and mesh-connected systems. 
In this approach each node is associated with a safety level,
which is an approximate measure of the number and distribution 
of faulty nodes in the neighborhood.  The safety level can be used 
to determine routing feasibility as well as to provide necessary 
information to facilitate optimal routing. Among irregular
networks, we discuss the construction of a connected dominating
set to support dynamic routing in ad-hoc wireless networks. 

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*********************************************************************** 
* Dr. Hong Shen          School of Computing & Information Technology * 
* Associate Professor of                          Griffith University *
*   Computer Science            Nathan, Brisbane, QLD 4111, AUSTRALIA *
* Research Director of                         Phone: +61 7 3875 5028 *  
*   Parallel Computing Unit                      Fax: +61 7 3875 5051 *
* Email: hong@cit.gu.edu.au       WWW: http://www.cit.gu.edu.au/~hong *
***********************************************************************