Senior Hardware Design-System/Board Level Networking

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From: Active Staffing
Date: Fri, 26 Feb 1999 00:00

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Location: Santa Clara

Salary: D.O.E. + bonus + stock options

Start Date: Immediately

You will participate in the earliest stage of building
the company.

You will be the Senior Hardware Design Engineer
handling high-speed board-level design from schematic
capture to board assembly.

Experience with high-speed processor, TDM (1/E1),
Ethernet, Frame Relay, IP and/or ATM is preferred.
Experience from specification to block diagram, timing
analysis, schematic capture, and layout is needed.
Design experience implementing algorithms in FPGA or
ASIC using VHDL or Verilog is required.

Contact:
Kim Vu
Active Staffing
tel. 408-245-1400
fax  408-245-5268
kvu@activestaff.com

Technical Details

Message-ID: <36D71823.E8D3D935@activestaff.com>

Path: arc1-ca.pugleaf.net!unknown!not-for-mail

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From: Active Staffing <tvu2@activestaff.com>
Subject: Senior Hardware Design-System/Board Level Networking
Date: 1999/02/26
Message-ID: <36D71823.E8D3D935@activestaff.com>
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