Article View: borland.public.cppbuilder.nativeapi
Article #7565Re: Accessing same variable from multiple threads
From: Alan Bellingham
Date: Thu, 20 Jan 2005 00:58
Date: Thu, 20 Jan 2005 00:58
52 lines
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3621 bytes
Bob Gonder <notbg@notmindspring.invalid> wrote: >I disagree. The alignment should be inconsequential. >If CPU A is doing a mov (one cpu instruction) on 2 dwords (due to >misalignment), then those 2 dwords should be locked by the memory >handler (as it does an internal read/modify/write), so that CPU B >can't access them. Even if the two parts are in two different pages, and the second causes a page fault? Or will the memory handler lock cause the page fault and subsequent frantic activity as the page gets loaded? >Only case where it should be a problem is if the cpu has to update the >value in two parts, as in an int64. Yes, for those. (And some may well consider an __int64 as a primitive.) >That is the current state in single-cpu86-land. >Interrups (other than instruction faults) occur between instructions. >LOCK is used to lock memory (and interrupts) for what the book calls >"indivisible read/modify/write cycles" (where the data physicaly >leaves and reenters the memory module). OK. I've not read the Intel docs on this. >No, except for internal faults, the current instruction is completed >before each interrupt. Other processors, however, may access the same >memory during the course of another processor's instruction (as in >INC). Thus the LOCK modifier. Single-instruction stores such as MOV >however, must be "safe" or else Intel wouldn't have made LOCK illegal >on them (apparently, it was legal until the 386 came out). Interesting. I suppose that was the sane course of action. >>However, if I remember my assembler, there are some instructions that go >>on for a potential lifetime by CPU clock cycle standards, so maybe it >>does. > >That's one of the reasons we don't have "real" real-time os's. >DIV is the longest I know of (other than FP, but they don't count) at >50 to 100 cycles. But BOUNDS, IRET with taskswitch, run 2-300, but I'd >think the'yd be at the start or end of an interrupt, and not be >subjected to further interrupts. Isn't there a REP instruction that continues until CS or something reaches zero? Alan Bellingham -- Me <url:mailto:alanb@episys.com> <url:http://www.doughnut.demon.co.uk/> ACCU - C, C++ and Java programming <url:http://accu.org/> The 2004 Discworld Convention <url:http://dwcon.org/>
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X-Google-Thread: 10cc67,4809cdd9a7828fa7 X-Google-Attributes: gid10cc67,public X-Google-Language: ENGLISH,ASCII-7-bit From: Alan Bellingham <alanb@episys.com> Newsgroups: borland.public.cppbuilder.nativeapi Subject: Re: Accessing same variable from multiple threads Date: Thu, 20 Jan 2005 00:58:35 +0000 Reply-To: alanb@episys.com Message-ID: <5a0uu015uqqt50bu5knqa704tkhkmuebia@4ax.com> References: <41edea6b@newsgroups.borland.com> <41ee3727$1@newsgroups.borland.com> <41ee742e$1@newsgroups.borland.com> <41ee8f57$1@newsgroups.borland.com> <qu9tu0hgv4gqnlvv65nqq70ua4v73jv0mu@4ax.com> <ktatu01v81kub73v28uhkhp1ccrl4ct9j6@4ax.com> <qmmtu09mtj1dnckicq85cq03k9ro6aqsje@4ax.com> <ddotu0t652i1q3a5ulnnt0c78ocr25vuae@4ax.com> X-Newsreader: Forte Agent 2.0/32.652 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 62.49.31.105 X-Trace: newsgroups.borland.com 1106182719 62.49.31.105 (19 Jan 2005 16:58:39 -0800) Lines: 52 Path: arc1-ca.pugleaf.net!g2news1.google.com!news1.google.com!proxad.net!proxad.net!194.159.246.34.MISMATCH!peer-uk.news.demon.net!kibo.news.demon.net!demon!194.74.65.66.MISMATCH!news-peer0-test!news-peer-test!btnet!newsfeed.bt.es!caladan.landsraad.net!newsgroups.borland.com!not-for-mail