🚀 go-pugleaf

"Alan Bellingham" <alanb@episys.com> wrote in message
news:qmmtu09mtj1dnckicq85cq03k9ro6aqsje@4ax.com...

> Nope - because as Gambit points out, your primitive may require
> more than one access to read or write. At least on the x86
> architecture, which doesn't insist on DWORDs being DWORD aligned.
>
> In such a case, it ain't atomic any more.

Correct.  If a value is not aligned properly, it may take multiple
read/write operations to access the value.

> My point was that I didn't think the scheduler would interrupt
> during the read or the write.

It can for misaligned values.

> But I'm not sure how low it goes, and whether it will interrupt
> during what is apparently a single CPU operation.

Atomic operations cannot be interrupted.  There is no way they could be.
The scheduler needs CPU cycles to perform its work, just like any other
task, but the CPU performs one operation at a time and atomic operations use
a single CPU cycle.

> However, if I remember my assembler, there are some instructions that
> go on for a potential lifetime by CPU clock cycle standards, so maybe
> it does.

Some instructions do take up multiple CPU cycles, and as such can be
preempted by the scheduler.  That is why task switching preserves all
current register values during the switch.  When the scheduler switche back,
the preempted operation can pick up where it left off and it never knows
that it was interrupted.  The problem occurs when operations are accessing
non-stack memory, which can be altered when the tasks switched around.  The
preempted operation has now way of knowing that the memory it was accessing
had been altered while the operation was suspended.


Gambit