Tristate Inverter

Article View: can.vlsi

Article #145

#145

From: Jacky Chen Loong Sang
Date: Thu, 27 Jan 2000 00:00

18 lines
1461 bytes

Hello,
        Does anyone know what is HIGH IMPEDANCE meant in tristate
inverter when its Enable input is LOW.
        I use tristate inverter to select one of the few function blocks
in a time. I'm now simulating one of the function block with spice3 that
work together with magic VLSI design tool.When Enable is LOW, what
waveform will be shown in the output ?
        The resulted waveform that I got is ---when Enable is LOW, the
output waveform is follow the previous output.
        I'm not sure whether my circuit right or not. I've built the
tristate inverter as 2 pMOS above of 2 nMOS. One of the pMOS and nMOS
are connected to input, A, the other pMOS is connected to /Enable (
inverted input of Enable) and the other nMOS is connected to Enable.
        Am I using the correct method to select function?
        Thanks for your kindness to teach me.

Sincerely,
Jacky Chen

Technical Details

Message-ID: <38900CF4.BE2CE446@tm.net.my>

Path: arc1-ca.pugleaf.net!unknown!not-for-mail

Show Full Headers

Complete Article Headers

X-Google-Language: ENGLISH,ASCII-7-bit
X-Google-Thread: f70d0,11dd33a1ed432faf,start
X-Google-Attributes: gidf70d0,public
From: Jacky Chen Loong Sang <clsjack@tm.net.my>
Subject: Tristate Inverter
Date: 2000/01/27
Message-ID: <38900CF4.BE2CE446@tm.net.my>
X-Deja-AN: 578233720
X-NNTP-Posting-Host: wmu-54-94.tm.net.my
Content-Transfer-Encoding: 7bit
X-Accept-Language: en
Content-Type: text/plain; charset=us-ascii
X-Trace: 27 Jan 2000 17:17:00 +0800, wmu-54-94.tm.net.my
Organization: TMnet Malaysia
MIME-Version: 1.0
Newsgroups: can.vlsi