🚀 go-pugleaf

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CANADIAN MICROELECTRONICS CORPORATION/SOCIETE CANADIENNE DE MICRO-ELECTRONIQUE
 
NEWS IN MICROELECTRONICS                     Volume 8, Number 44, July 9, 1996
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TODAY'S ISSUE: 0.5-micron CMOS (CMOSIS5) Design Kit V1.0 for Cadence 
               Analog Artist
                                   <<<<>>>>

The first fabrication run coordinated by CMC for designers who wish to use the
0.5-micron CMOS (HP) technology is scheduled for September 25, 1996. To help
designers prepare for the run, CMC is now releasing a design kit for Cadence
Analog Artist. The attached Microelectronics Technology Bulletin describes the
CMOSIS5 kit and where to obtain it.
 
As noted in our June 27th message, all CMC university Members who wish to have
access to the CMOSIS5 technology must sign a MOSIS Customer Agreement and
designers who want to apply for space on the September 25th run must submit a
Request for Manufacturing Resources to CMC by July 31, 1996. Remember there 
will be no Last Minute Club service available for CMOSIS5. Contact Mirielle
Keeling (keeling@cmc.ca) for information on the Customer Agreement and RFMR
process.
 
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CANADIAN MICROELECTRONICS CORPORATION/SOCIETE CANADIENNE DE MICRO-ELECTRONIQUE
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                **** MICROELECTRONICS TECHNOLOGY BULLETIN ****
 
Technology:  	0.5-micron CMOS (CMOSIS5) Design Kit V1.0 for Cadence 
                Analog Artist
Source: 	MOSIS, HP, Canadian Microelectronics Corporation 
Release Date:	July 8, 1996
ID Code:        SE0235
Status:   	Supported

Description:    A new design kit developed for Cadence Analog Artist and for
                the HP 0.5-micron CMOS technology, arranged through MOSIS.
                The flavour being provided to CMC is a triple metal, 
                single poly CMOS process allowing a minimum drawn feature 
                size of 0.6 micron.

                The design kit supports the following functionality:

                - Schematic capture, physical layout, DRC, layout extraction
                  (with/without parasitic capacitance), abstract generation.
                - HSPICE simulation with level3 or level13 models.
                  Spectre simulation with level3 or bsim1 models.
                - Verilog simulation (without timing information because 
                  back annotation capability is not yet in place).
                - Cell Ensemble P&R with the supplied standard cells.
                - LVS (layout versus schematic).

                There are four technology-specific libraries:  cmosis5,
                cmcpads, mosispads and hcells.  Descriptions of the
                components in the libraries can be found in the design kit
                documentation.  Documentation describing the basic flows for 
                place and route, LVS and simulation is included.

                This design kit is intended for use with the CMC Generic 
                Technology Environment for Cadence V1.4.

Keywords:       0.5 micron, MOS, MOSIS, HP, triple metal, CMC

Suggested Enhancements:  See README file and design kit documentation

Known Problems and Limitations: See README file and design kit documentation
 
Release Categories: 
                CATEGORY 1: MEMBER UNIVERSITIES
                            Available to Member universities 
                            once distribution requirements are met.

Distribution Requirements:
                CATEGORY 1: MEMBER UNIVERSITIES
                            Equipment Loan Agreement & MOSIS Customer
                            Agreement 
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This technology is available from the CMC FTP server, keeper.cmc.ca

Required files:
Tools_Tech/Design_Kits/CMOSIS5/Cadence/V1.0
2941 Jul  9 12:25 LICENSE
7073 Jul  9 12:25 README

Tools_Tech/Design_Kits/CMOSIS5/Cadence/V1.0/data
5945968 Jul  9 13:49 cds_cmosis5.1.0.tar.Z.X

Once the MOSIS Customer Agreement has been executed, decryption keys will be
required to obtain this release (contact Mirielle Keeling, keeling@cmc.ca). 
When you retrieve the technology, please be sure to read the LICENSE file
included with the release.

Information on this technology is also available on CMC's World Wide Web
server at: http://www.cmc.ca/Tools_Tech/Design_Kits/CMOSIS5/Cadence/V1.0

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MICROELECTRONICS TECHNOLOGY  BULLETINS describe available technology  that can
be sourced through Canadian Microelectronics Corporation, its Members or its
suppliers.   Examples include design cells, CAD software, technical reports or
fabrication technology.   The bulletin  provides  basic information about  the
status of  the technology  and  conditions  of  access.   For more information
contact:       Jane Milne               Network:    milne@cmc.ca
					Telephone:  (613) 530-4658
                                        Facsimile:  (613) 548-8104
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CANADIAN MICROELECTRONICS CORPORATION/SOCIETE CANADIENNE DE MICRO-ELECTRONIQUE
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