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Article #302Re: 7 input nand (1.2u)
From: J.A. Barby
Date: Sun, 14 Mar 1993 03:03
Date: Sun, 14 Mar 1993 03:03
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In article <dmartin.732045193@femto.engr.mun.ca>, dmartin@pico.engr.mun.ca (Dan Martin) writes: > Hi, > > I am doing a term project using 1.2u CMOS4S technology. The > standard cells only go up to 4-input nands, but I need a 7-input nand. > I am having problems finding the optimal widths of the nmos and pmos > transistors. I also have to make an 12-input nand. > Are these values already documented somewhere, or does anyone know > how to calculate them? Thanks in advance. > > Dan Martin For propogation delay reasons, you do not want to go over 4-input in a CMOS4S gate. You break it into multilevel logic as 2 propogation delays for 4-input (or less) gates is less than propogation delays for a 7-input or 12-input gates. -- Jim Barby <jabarby@vlsi.UWaterloo.ca> VLSI Group, University of Waterloo, Waterloo, Ontario, Canada, N2L 3G1 519-885-1211x3995, FAX 519-746-5195
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: f70d0,4267d1f0337e8399 X-Google-Attributes: gidf70d0,public X-Google-ArrivalTime: 1993-03-13 23:56:31 PST Newsgroups: can.vlsi Path: arc1-ca.pugleaf.net!sparky!uunet!europa.eng.gtefsd.com!howland.reston.ans.net!zaphod.mps.ohio-state.edu!rpi!utcsri!utnut!torn!watserv2.uwaterloo.ca!sun3.vlsi.uwaterloo.ca!sun5.vlsi.uwaterloo.ca!jabarby From: jabarby@sun5.vlsi.uwaterloo.ca (J.A. Barby) Subject: Re: 7 input nand (1.2u) Message-ID: <C3uz5n.8Jq@sun3.vlsi.uwaterloo.ca> Sender: news@sun3.vlsi.uwaterloo.ca Organization: University of Waterloo References: <dmartin.732045193@femto.engr.mun.ca> Date: Sun, 14 Mar 1993 03:03:22 GMT Lines: 20