Bus terminals in Edge and Verilog netlist.

Article View: can.vlsi

Article #313

#313

From: Christian Burt Berel S.
Date: Thu, 05 Aug 1993 06:20

19 lines
1297 bytes

Newsgroups: can.vlsi,comp.lang.verilog,comp.cad.cadence
Subject: world
Summary: 
Followup-To: 
Distribution: can
Organization: University of Regina, SK, Canada
Keywords: 

Hi,

Is there any way to tell the Edge Verilog Netlister to use vectored
registers/wires for the bus terminals in an Edge schematic ?

I would also like to know about the same thing in Cadence 4.2.

Thank you.

Burt.
(bbsc@cs.uregina.ca)

Technical Details

Message-ID: <1993Aug05.062059.1073228@sue.cc.uregina.ca>

Path:

arc1-ca.pugleaf.net!gmd.de!rrz.uni-koeln.de!news.dfn.de!darwin.sura.net!math.ohio-state.edu!sdd.hp.com!elroy.jpl.nasa.gov!decwrl!tribune.usask.ca!sue!mercury.cs.uregina.ca!bbsc

Show Full Headers

Complete Article Headers

X-Google-Language: ENGLISH,ASCII-7-bit
X-Google-Thread: 10270d,d0d32bba118a2558,start
X-Google-Attributes: gid10270d,public
X-Google-Thread: f70d0,d0d32bba118a2558,start
X-Google-Attributes: gidf70d0,public
X-Google-Thread: 112e4c,d0d32bba118a2558,start
X-Google-Attributes: gid112e4c,public
X-Google-ArrivalTime: 1993-08-05 12:02:42 PST
Newsgroups: can.vlsi,comp.lang.verilog,comp.cad.cadence
Path: arc1-ca.pugleaf.net!gmd.de!rrz.uni-koeln.de!news.dfn.de!darwin.sura.net!math.ohio-state.edu!sdd.hp.com!elroy.jpl.nasa.gov!decwrl!tribune.usask.ca!sue!mercury.cs.uregina.ca!bbsc
From: bbsc@mercury.cs.uregina.ca (Christian Burt Berel S.)
Subject: Bus terminals in Edge and Verilog netlist.
Sender: news@sue.cc.uregina.ca
Message-ID: <1993Aug05.062059.1073228@sue.cc.uregina.ca>
Date: Thu, 05 Aug 1993 06:20:59 GMT
Organization: University of Regina, SK, Canada
Lines: 19