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CCVLSI'92
CCITGE'92
October 18-20, Chateau Halifax
Halifax, Nova Scotia, Canada

Canadian Conference On Very Large Scale Integration
Conference Canadienne Sur L'integration a Tres Grande Echelle

Conference Highlights ...... line  14
Detailed Program ........... line 118
Preregistration Form ....... line 360
Hotel Reservation Form ..... line 397

============== Conference Highlights =========================================

Sunday, October 18	Pre-Conference Meeting
	Baronet Room, Chateau Halifax
	Lecturer: John Roberts, President & C.E.O. of
		Strategic Microelectronics Consortium.
	The presentation will focus on the Strategic Microelectronics
	Consortium's plans and the role CMC and universities can play.
	The Pre-Conference Meeting will run from 2:00 pm to 4:00 pm.

Sunday, October 18	Reception
	Baronet Room 4, 5 & 6, Chateau Halifax
	The reception is from 7:00 pm to 9:00 pm.

Monday, October 19	Lunch
	Bluenose Room, Chateau Halifax
	Sponsored by Northern Telecom and Bell-Northern Research.
	The speaker will be Dr. David Lynch, Director of Silicon Design, BNR

Monday, October 19	Panel Discussion
	Baronet Room, Chateau Halifax
	Topic: Industry /University Collaboration Models
	The panel will discuss successful models and possible directions for
	the CMC.  Panelists confirmed to date include: John Roberts, President
	& C.E.O. of Strategic Microelectronics Consortium; and Robert Fournier,
	Associate Vice President (Research) and Chairman of Nova Scotia Council
	of Applied Science & Technology.
	The Panel Discussion commences at 7:00 pm.

Tuesday, October 20	Lunch
	Bluenose Room, Chateau Halifax
	Presentation on CMC Business Planning (tentative)

Displays by conference sponsors and selected
	equipment suppliers

The Conference terminates at 3:15 pm on Tuesday to allow ample time to catch
late afternoon flights to Montreal, Ottawa, Toronto and other points west.

There will be a $2,000 prize for the Best Paper Award. The award will be
judged on the technical merit of both the initial submitted version of the
paper and the final version of the paper as well as the lecture or poster
presentation.

==============================================================================

Co-sponsors
	Canadian Microelectronics Corporation
	Applied Microelectronics Institute
	Technical University of Nova Scotia
	Northern Telecom Electronics Ltd.
	Bell-Northern Research Ltd.
	Canadian Semiconductor Design Association
	Strategic Microelectronics Consortium
	Alberta Microelectronic Centre
	Mitel Corporation
	Gennum Corporation
	MPR Teltech Ltd.
	Information Technology Research Centre
	Telecommunications Research Institute of Ontario
	Micronet

Chateau Halifax, Halifax, Nova Scotia, Canada
October 18-20, 1992

Organizing committee chair
	Dr. D. Pincock
	Applied Microelectronics Institute
	Halifax, Nova Scotia, Canada

Technical program committee chair
	Dr. J.A. Barby
	Electrical and Computer Engineering
	University of Waterloo
	Waterloo, Ontario, Canada

Technical Program Committee
	D. Agnew, Bell-Northern Research
	J. Barby, University of Waterloo
	G. Birtwistle, University of Calgary
	M. Copeland, Carleton University
	G. Jullien, University of Windsor
	A. Parameswaran, Simon Fraser University
	D. Pincock, Applied Microelectronics Institute
	Y. Savaria, Ecole Polytechnique
	J. Seary, Canadian Microelectronics Corporation
	M. Snelgrove, University of Toronto
	
Address correspondence to:
	Jolien Barresi
	Applied Microelectronics Institute
	1046 Barrington Street
	Halifax, Nova Scotia, Canada  B3H 2R1
	Phone (902) 421-1250
	Fax (902) 429-9983
	barresi@appliedmicro.ns.ca

Registration will be held on Sunday, October 18th from 12:00 noon to 9:00 pm
and on Monday, October 19th from 8:00 am to 1:00 pm in the Baronet Room,
Chateau Halifax.

A pre-registration and hotel reservation forms are available for your
convenience at the end of this program.

============== detailed program ==============================================

Session 1	Baronet Rooms 1 & 2
Yvon Savaria, Chair

8:00 - 8:10
Welcoming Remarks

8:10 - 8:35
1.1  A High Level VLSI Design for Ultra Dense Instruction Set Computer
	Architectures.
	O. S. Schoepke (University of Bath, U.K.)

8:35 - 9:00
1.2  Strategies for Synthesis of Instruction-Set Processors.
	J.D. Tompkins, W. Robertson (Technical University of Nova Scotia)

9:00 - 9:25
1.3  An Address Bit-Shifting Microcontroller for ASICs.
	T. Le, J. Knight (Carleton University)

9:25 - 10:25
Poster Session 1	Baronet Rooms 4, 5 & 6

10:25 - 10:50
1.4  VLSI Design of a M-path Decoder IC Suitable for Bidirectional Decoding of
	Convolutional Codes.
	M. Chalifoux, M. Nguyen, Y. Savaria, J. Belzile, D. Haccoun
	(Ecole Polytechnique de Montreal)

10:50 - 11:15
1.5  On Area Efficient Systolic Interconnection Networks.
	G. Panneerselvam (University of Calgary),
	S. Bandyopadhyay, G.A. Jullien (University of Windsor)

11:15 - 11:40
1.6  Performance Analysis and Design of Optimized Static Random Access Memory
	(SRAM).
	D. Jahangir, B. Haroun, A.J. Al-Khalili (Concordia University)

------------------------------------------------------------------------------

11:40 - 1:40
Lunch - Bluenose Room
Sponsored by Northern Telecom and
Bell-Northern Research
The speaker will be Dr. David Lynch, Director of Silicon Design, BNR.

------------------------------------------------------------------------------

Session 2	Baronet Rooms 1 & 2
Jim Seary, Chair

1:40 - 2:05
2.1  Delay and Current Estimation in CMOS Gates Using Collapsing.
	A. Nabavi-Lishi, N.C. Rumin (McGill University)

2:05 - 2:30
2.2  An Empirical Timing Characterization Method and its Application to CMOS
	Logic Circuits.
	R.S. Shum, M.C. Lefebvre (Carleton University)

2:30 - 2:55
2.3  Verifying an Instruction Cache using the Voss Verification System.
	C.H. Seger, J. Chow, W. Low, B. Tsuji (University of British Colombia)

2:55 - 3:55
Poster Session 1 (Continued)
Baronet Rooms 4, 5 & 6

3:55 - 4:20
2.4  An Approach for Behavioral Verification of Circuit Designs.
	M. Langevin, E. Cerny (Universite de Montreal)

4:20 - 4:45
2.5  Pseudo-Random Vectors Can Achieve Deterministic Initialization.
	F. Darlay, M. Soufi, Y. Savaria, B. Kaminska
	(Ecole Polytechnique de Montreal)

4:45 - 5:10
2.6  Design of CMOS Complex Gates for Multiple Faults Testability.
	F. Darlay (Ecole Polytechnique de Montreal)

------------------------------------------------------------------------------

7:00 - 9:00
Panel Discussion: "Industry/University Collaboration Models"
Panelists confirmed to date include
 John Roberts, President & C.E.O. of Strategic Microelectronics Consortium
 Robert Fournier, Associate Vice President (Research) and Chairman of
		  Nova Scotia Council of Applied Science & Technology.

------------------------------------------------------------------------------

Session 3A	Baronet Room 1
Miles Copeland, Chair
Session 3B	Baronet Room 2
David Agnew, Chair

8:00 - 8:25
3A.1  A Wide-Range Tunable BiCMOS Transconductor.
	A. Shoval, D.A. Johns (University of Toronto),
	W. M. Snelgrove (Carleton University)
3B.1  Interior Point Methods for Finding Netlist Partitions.
	A. Singh, K. Ponnambalam, A. Vannelli (University of Waterloo)

8:25 - 8:50
3A.2  Gain Enhancement in GaAs MESFET Opamps.
	S. Xiao, R.Y.V. Chik, C.A.T. Salama (University of Toronto)
3B.2  A Partitioning Algorithm for Large Graphs.
	M. Meknassi, E.M. Aboulhamid, E. Cerny (Universite de Montreal)

8:50 - 9:15
3A.3  A High Stability CMOS Voltage Reference.
	J.Y. Zhu (Shanghai), W. Rasmussen, S. Richard (Universite de Sherbrooke)
3B.3  Optimal Register Allocation and Binding in Behavioral Synthesis.
	T.C.Wilson, B. Halley (University of Guelph),
	R. Deadman (Mitel Corporation), D.K. Banerji (University of Guelph)

9:15 - 10:15
Poster Session 2	Baronet Rooms 4, 5 & 6

10:15 - 10:40
3A.4  A Low-Power High-Speed Analog Circuit Technique.
	D.G. Nairn (Queens University)
3B.4  Timing-Driven Routing Segment Assignment in FPGAs.
	B. Fallah, J. Rose (University of Toronto)

10:40 - 11:05
3A.5  A Pipelined Current-Mode CMOS Analog-to-Digital Converter.
	R.A. Brooks, D.G. Nairn (Queens University)
3B.5  The Implementor Subsystem in DAME:  Using OASIS to Complete the Design
	Automation of Microprocessor-based Systems.
	M.A. Escalante, N.J. Dimopoulos, D.M. Miller, K.F. Li, E.G. Manning
	(University of Victoria)

11:05 - 11:30
3A.6  Floating Gate MOS Device as an Analog Element for Analog Trimming.
	W. Gao (University of Toronto), W.M. Snelgrove (Carleton University)
3B.6  Efficient Clock-Pin Assignment for Synchronous Systems.
	W.A. Khan, M. Hossain, N.A. Sherwani (Western Michigan University)

------------------------------------------------------------------------------

11:30 - 1:00
Lunch - Bluenose Room
Presentation on CMC Business Planning (tentative)

------------------------------------------------------------------------------

Session 4	Baronet Rooms 1 & 2
Martin Snelgrove, Chair

1:00 - 1:25
4.1  CMOS Photo-Sensitive Device with Multiresolution Edge Detection
	Capability for Computer Vision.
	M. Tremblay, D. Poussart (Universite Laval)

1:25 - 1:50
4.2  CMOS Photodetector with Built-In Light Adaptation Mechanism.
	V. Ward, M. Syrzycki, G. Chapman (Simon Fraser University)

1:50 - 2:15
4.3  A VLSI Implementation of Feedforward Neural Networks with Learning.
	L.Song, M.I. Elmasry, A. Vannelli (University of Waterloo)

2:15 - 3:15
Poster Session 2 (Continued)
Baronet Rooms 4, 5 & 6

------------------------------------------------------------------------------

Poster Session 1    Monday, October 19
Doug Pincock, Chair

P1.1  FiltorX: Computer-Aided Filter Design and Industry.
	C. Ouslis (University of Toronto), S.C. Good (Mitel Corporation),
	M. Snelgrove (Carleton University), A. S. Sedra (University of Toronto)

P1.2  Multiple Stuck-At Fault Diagnosis in Logic Circuits.
	Y. Karkouri, E.M. Aboulhamid (Universite de Montreal)

P1.3  A Modified Maze Routing Algorithm for Leaf Cell Synthesis.
	D.F. Skoll, M.C. Lefebvre (Carleton University)

P1.4  A VLSI Implementation of a Parallel Analog Laplacian of Gaussian Filter
	with Multiple Resolution Levels.
	M. d'Anjou, M. Tremblay, D. Laurendeau (Universite Laval)

P1.5  Stochastic Arithmetic Implementations of Neural Networks.
	J.A. Dickson, R.D. McLeod, H.C. Card (University of Manitoba)

P1.6  Switched-Capacitor Weight Storage Elements with Refresh Learning Scheme
	for ANN Implementation.
	B. Maundy, E.I. El-Masry (Technical University of Nova Scotia)

P1.7  Kohonen Self-Organizing Maps for FPGA Placement.
	D.C. Blight, R.D. McLeod (University of Manitoba)

P1.8  Synthesis and Implementation Tradeoffs of Digital VLSI Neural Networks.
	B. Haroun, E. Torbey, A. Zaidi (Concordia University)

P1.9  Probabilistic Design of Large Scale Linear Circuits Using Automatic
	Formulation of Moment Equations.
	W.F. Curi, K. Ponnambalam (University of Waterloo)

------------------------------------------------------------------------------

Poster Session 2    Tuesday, October 20
Doug Pincock, Chair

P2.1  VLSI Design of a Digital Architecture for Quadrature Mirror Filter Banks.
	S.R. Pillai, W. Robertson, W. Phillips
	(Technical University of Nova Scotia)

P2.2  A Local Comparison Algorithm for VLSI Circuit Verification.
	X. Liu, A.G. Jost (Technical University of Nova Scotia)

P2.3  Combinational Logic Synthesis by Two-Place Decomposition and
	Autocorrelation Techniques.
	R. Tomczuk, D.M. Miller (University of Victoria)

P2.4  Electroless Plating for Commercial CMOS-Fabricated Sensors and
	Micromachines.
	P.G. Glavina, M. Parameswaran, R.F. Frindt (Simon Fraser University)

P2.5  Steiner Tree Approximation Using Neural Networks.
	I. Bennour, J. Cloutier (Universite de Montreal)

P2.6  Current-mode CMOS Realization of MVL Operators.
	A.K. Jain, R.J. Bolton, M.H. Abd-El-Barr, V. Fortugno
	(University of Saskatchewan)

P2.7  URCAD:  A Systolic Array Design Environment.
	Y. Yan, A.G. Law, J.H. Weston, C.N. Zhang (University of Regina)

P2.8  The Partitioning of Linear Registers for Testing Applications.
	E. Kontopidi, J.C. Muzio (University of Victoria)


==============================================================================

============== conference registration ========================================
Please complete and return form to:

CCVLSI '92 Secretary
Applied Microelectronics Institute
1046 Barrington Street
Halifax, Nova Scotia  B3H 2R1

Hotel Reservations must be returned to Chateau Halifax by October 9, 1992.


Please print


Family Name	Common Name

Affiliation

Correspondence mailing address	home	office
Phone

Registration Fee - $160
Full-time Student - $50
(Registration fee includes the reception on October 18, lunch on
October 19 and 20, Proceedings and Pre-Conference Meeting)

Remittance:
I will pay the registration fee at the door.
I have enclosed       payable to the order of Applied Microelectronics
Institute.
(Fee - $160; Students - $50)

Date		     Signature


==============================================================================

============== hotel reservation =============================================
Registration Form    CCVLSI HOTEL RESERVATIONS

CHATEAU HALIFAX
Scotia Square
1990 Barrington Street
Halifax, Nova Scotia
Canada B3J 1P2


Delegate Name:
Address:
City:
Province:			Postal Code:
Arrival Date:		Arrival Time:
Departure Date:

Single Room $105		Double Room $105

Additional charge of $15 per person for triple or quad accommodations.

Request non-smoking room (subject to availability)

Sharing room with

RESERVATIONS ARE HELD
UNTIL 6:00 pm ONLY UNLESS
GUARANTEED WITH A CREDIT
CARD OR DEPOSIT

We accept:  VISA, Mastercard,
American Express, EnRoute,
Diners Club, & JCB Card

Please guarantee my reservation to my credit card:

Card Name:                        Expiration:
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Deposit is refundable if cancellation is received 48 hours in advance of
schedule arrival.  Be sure to record your cancellation number.

CHECK IN TIME IS 4:00 pm
CHECK OUT TIME IS 1:00 pm

==============================================================================

-- 
 Jim Barby  <jabarby@vlsi.UWaterloo.ca>
 VLSI Group, University of Waterloo, Waterloo, Ontario, Canada, N2L 3G1
 519-885-1211x3995, FAX 519-746-5195