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                                     COLLOQUIUM

                University at Albany - State University of New York

                            Computer Science Department

                Computation of Signal Delays in General RC Networks

                                Juan Carlos Hidalgo

                           Department of Computer Science
                                    SUNY Albany

                   Wednesday, March 10, 1993 at 11:15 AM in LI-98

                                      ABSTRACT

                 Time considerations are crucial to  correctly  model  common
            CMOS designs since crude approximations often result in incorrect
            or incomplete behavior. Race conditions are  a  good  example  of
            time sensitive situations.  If models do not capture or correctly
            simulate these conditions, false behavior can be predicted.

                 In this talk we present a model for signal delay computation
            in  CMOS designs. We assume that the switch level behavior of the
            circuits is modeled as sequences of RC networks.  The strength of
            the paradigm is its generality and simplicity.  Our definition of
            delay  is  applicable  to  RC  meshes  with  potential  resistive
            attenuating  paths to ground.  Our algorithms can also be applied
            to undriven circuits (static charge sharing)  and  circuits  with
            initial  charge.  To compute the delays, each node in the network
            is explored locally to derive a system  of  sparse  linear  equa-
            tions.  The solutions of the system are delay values based on the
            Elmore time constant at each point in the circuit.