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                      Note Room is Hamerschlag Hall, 1112
                      Date is Tuesday, November 9, 1999
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                          ECE DISTINGUISHED LECTURE

                              DR. FRED POLLACK
                        MICROPROCESSOR PRODUCTS GROUP
                              INTEL CORPORATION

                         TUESDAY, NOVEMBER 9, 1999
                                  4:00 PM
                         HAMERSCHLAG HALL, ROOM 1112
                          Refreshments at 3:30pm
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          ``New Microarchitecture Challenge in the Coming Generations
                       of CMOS Process Technologies''


                                   ABSTRACT
Over the last 15 years, CMOS scaling simplified the task of the
microprocessor architect. With each new process technology, frequency
increased by ~50%, and transistor density increase by 100%. Also, the
improvements in manufacturing technology (larger wafers and higher yields)
allowed for increasing die sizes without increasing cost. Projections of
die sizes of 1 square inch or higher were common.

However, the end of these easy times is in sight, and several new challenges
are facing the architect. Die size is no longer going to be limited by
equipment or manufacturing cost, but rather by power. To date the approach
has been to lower voltage with each process generation. But as voltage is
lowered, leakage current and energy increase, contributing to higher power.
And the problems extend beyond power dissipation to power delivery/
distribution and increasing power density.

This talk will first look at the historical trends of CMOS process
technology in the context of past microprocessors. It will then look at
the implications of continued CMOS scaling, as described above, and the
new challenges they pose.

Microarchitecture techniques that have exacerbated the power problem will
also be covered. Finally, the talk will describe some of the
microarchitecture directions that may lead to more power-efficient and
cost-efficient microprocessors.

                                      BIO
Fred Pollack is the Director of the Microprocessorearch Labs (MRL), which has
research projects in Santa Clara, Calif.; Hillsboro, Ore.; Haifa, Israel;
and Beijing, China. MRL focuses in several different areas including
computer architecture, compilers, circuits, graphics, video, security, and
new computing models.

>From mid-1992 to early 1999, Fred was director of the MAP group in MPG.
This division is responsible for all Intel platform architecture and
performance analysis. In this role, he was also responsible for directing
the planning of Intel's future microprocessors. From mid-1990 to mid-1992,
he was the Architecture Manager for the Pentium( Pro microprocessor. He
joined Intel in 1978. Earlier assignments included manager of the i960
architecture and chief architect for an advanced object-oriented,
distributed operating system. In January of 1993, he was named an
Intel Fellow.