🚀 go-pugleaf

-----Original Message-----
Sent: Thursday, March 09, 2000 11:55 AM
To: 'tsuhan@ece.cmu.edu'
Cc: Gross, Rick
Subject: opportunities at Aware


Hi Tsuhan,
 How are you doing?  It's been a number of ICASSP's since I've seen
you.  From afar, looks like you're continuing to do interesting work on
multimedia.  I am writing because my colleague, Dr. Rick Gross (Senior VP of
Engineering Development), will be on campus at CMU next Friday (3/17) to
recruit DSP, ASIC, and communications engineers for Aware, for both
permanent positions and summer internships.  Our company is focussed on
physical layer broadband communications and ADSL in particular these days,
I'm running the IC design group (!).  Would you be able to circulate the
following blurb among your students or others who might be interested in
exploring careers at Aware?  They should be able to sign up for interviews
with the on-campus career office.  Thanks a lot for your help.

Best Regards,

Peter


Aware, Inc. is an elite team of technologists focussed on high-speed
telecommunications.  We are world leaders in ADSL systems design and
implementation, with active research efforts into next-generation
technologies including VDSL, home phone networking, and wireless LAN's.  Our
management team has developed a highly successful intellectual property (IP)
business model by which blue-chip semiconductor manufacturers license our
designs for inclusion in their IC products. Aware is located in Bedford,
Massachusetts, about 20 miles northwest of Downtown Boston.

 Our customers include Intel, Lucent Microelectronics, Siemens
Semiconductor, Analog Devices, NEC Electronics, and others.  The company is
14 years old and went public in 1996. We are profitable with $35 million in
cash reserves;  a very stable platform for continued growth and success.

 We have 120 employees (a majority are engineers and developers, 30 of them
Ph.D.'s) and are looking to hire another 30-40 engineers in the year 2000,
from the disciplines of ASIC Design, DSP Algorithm Development,
Communications System Engineering, and Analog and Digital Hardware Design.


ASIC Design Engineers

The engineer will specify, design, simulate, and synthesize ASIC's embodying
high-speed communications algorithms drawing on ATM, error-correcting codes,
and digital signal processing. Requires experience with VHDL or Verilog and
C languages, RTL design of ASIC's or FPGA's, logic synthesis, and
simulation.  Familiarity with verification methodologies, revision control,
static timing analysis, and physical design a plus.

DSP Software Engineers

Design and implement xDSL modem software in C and Assembly Language on DSP
chips.  Desire to work in real-time software and embedded systems
development; experience a plus.  Signal processing and telecommunications
background required.  The position demands a desire to work as a member of a
team in a fast paced, rapid growth environment for the design and
development of high-speed wireline communication systems.  MS required; PhD
a plus.

Communications Systems Engineer

Theoretical modeling and system design of broadband DSL transmission systems
using Matlab or SPW.  Strong background in algorithm development, signal
processing, digital modulation and information theory at the systems level
required.  An understanding of the transmission characteristics and noise
environment of the public telephone network a plus.  MS required, PhD a
plus.

Analog Hardware Engineer

Design ADSL hardware and reference designs.  Manage schematics, layout
contracting, hardware performance, DVT and release to manufacturing.
Understanding of communications systems involving discrete and integrated
analog components required.  Familiarity with D-A, A-D, op-amps and filter
design desirable.  Viewlogic, WVOffice, microprocessor and microcontroller
experience a plus.  BSEE required.

For more information, please view our website:
<http://www.aware.com/>