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Date: Fri, 20 Oct 2000 21:39:03 -0700 (PDT)
From: Mike Schlansker <schlansk@hpl.hp.com>
Subject: MICRO-33, December 10-13, 2000, Monterey, CA


************************************************************
                     Advance Program: MICRO-33
           International Symposium on Microarchitecture
                        December 10-13, 2000
                         Monterey California

                 Important date: November 15, 2000 �
               MICRO-33 Advance registration deadline

************************************************************

Dear colleague,

The organizing committee of MICRO-33 is pleased to announce the MICRO-
33 conference to be held in Monterey, California from Dec. 10 to Dec. 
13, 2000. MICRO represents the premier technical forum on 
microarchitecture. This forum is well attended by both academic and 
industrial experts on the design of microprocessors. For further 
information, visit the MICRO-33 web-site at: 
<http://www.microarch.org/micro33/>. 

MICRO-33 will be held in Monterey California. Beautiful Monterey 
offers the history of an old fishing town as well as spectacular views 
of the pacific ocean. The conference hotel, the Monterey Plaza Hotel, 
is a short walk from Fisherman's Wharf and the Monterey Bay Aquarium. 
The hotel has agreed to hold a limited number of rooms for conference 
attendees until November 9, 2000. The advance-registration deadline is 
Nov. 15, 2000.

So come to MICRO-33! Attend the workshops on: "Feedback-Directed and 
Dynamic Optimization", "Media Processors and DSPs", "Multithreaded 
Execution, Architecture and Compilation", and "Kool Chips"! Attend a 
high-quality technical program where a number of cutting-edge research 
papers on microarchitecture will be presented! The technical program 
contains 31 papers on topics including: architectures for instruction-
level parallelism, memory architecture, and low-power architecture. 
Enjoy the keynote speeches! Meet the experts in the field!

Students are strongly encouraged to attend Micro-33. The conference 
has received a record amount of funding for student travel grants 
through generous corporate sponsorship. Details regarding how students 
can apply for these grants will be made available on the MICRO-33 web 
site.

We apologize, in advance, for any redundant messages that you may
receive.

Thank you for your time in reading this message. If you have any 
further questions, you may contact me at: schlansk@hpl.hp.com.


 Michael Schlansker
 Micro-33 Program Chair
 Hewlett-Packard
 Palo Alto, CA.

************************************************************
MICRO-33 Advance Program

Sunday Dec. 10, Workshops:
     Feedback-Directed and Dynamic Optimization
     Media Processors and DSPs
     Multithreaded Execution, Architecture and Compilation
     Kool Chips

Keynote Speakers:
     o Darrell Boggs, Intel.
       "Breathing Life Into a Paper Tiger"

     o David Baker, BOPS
       "A Whole New Ballgame - Supercomputing on Two AA Batteries"

     o Phil Kuekes, Hewlett-Packard
       "Defect Tolerant Molecular Electronics: Algorithms, 
        Architectures, and Atoms"


8:00-9:30am, Monday Dec. 11, Welcome & First Keynote

10:00-12:00am, Monday Dec. 11, Memory Hierarchy
Session Chair: Ronny Ronen - Intel

"Eager Writeback - a Technique for Improving Bandwidth Utilization"
     Hsien-Hsin Lee, Gary Tyson, Matthew Farrens
"Silent Stores for Free"
     Kevin M Lepak, Mikko H Lipasti
"A Permutation-based Page Interleaving Scheme to Reduce Row-buffer 
Conflicts and Exploit Data Locality"
     Zhao Zhang, Zhichun Zhu , Xiaodong Zhang
"Predictor-Directed Stream Buffers"
     Timothy Sherwood, Suleyman Sair, Brad Calder

12:00-1:30 Monday Dec. 11, Lunch and Second Keynote

1:30-3:30pm, Monday Dec. 11, Superscalar Architecture
Session Chair: Gary Tyson -  University of Michigan

"On Pipelining Dynamic Instruction Scheduling Logic"
     Jared Stark; Mary D Brown; Yale N Patt 
"The Impact of Delay on the Design of Branch Predictors"
     Daniel A. Jimenez, Stephen W. Keckler, Calvin Lin
"Improving BTB Performance in the Presence of DLLs" 
     Stevan A Vlaovic, Edward S Davidson, Gary S Tyson 
"Efficient Checker Processor Design"
     Saugata Chatterjee, Christopher Weaver, Todd Austin

4:00-5:30, Monday Dec. 11, Compilation
Session Chair: Carol Thompson - Hewlett-Packard

"An Integrated Approach to Accelerate Data and Predicate Computations 
in Hyperblocks"
     Waleed Meleis, Alexandre Eichenberger, Suman Maradani 
"Accurate and Efficient Predicate Analysis with Binary Decision 
Diagrams" 
     John W Sias, Wen-mei W Hwu, David I August
"Modulo Scheduling for a Fully-Distributed Clustered VLIW 
Architecture"
     Jesus Sanchez, Antonio Gonzalez

Monday evening, Dec. 11, - Dinner

8:30-9:30am, Tuesday Dec. 12, Third Keynote 

10:00-12:00am, Tuesday Dec. 12, Accelerator Architecture
Session Chair: Tom Conte -  North Carolina State University

"Two-level Hierarchical Register File Organization for VLIW 
Processors"
     Javier Zalamea, Josep Llosa, Eduard Ayguade, Mateo Valero
"PipeRench Implementation of the Instruction Path Coprocessor"
     Yuan Chou, Pazhani Pillai, Herman Schmit, John P Shen
"Efficient Conditional Operations for Data-Parallel Architectures"
     Ujval J Kapasi, William J Dally, Scott Rixner, Peter R Mattson, 
     John D Owens, Brucek Khailany
"Flexible Hardware Acceleration for Multimedia Oriented 
Microprocessors"
     Frederik Vermeulen, Lode Nachtergaele, Francky Catthoor, Diederik 
     Verkest, Hugo De Man

12:00-1:30 Tuesday Dec. 12, Lunch

1:30-3:30pm, Tuesday Dec. 12, Low-Power Design
Session Chair: Rajiv Gupta -  University of Arizona

"Very Low Power Pipelines using Significance Compression"
     Ramon Canal, Antonio Gonzalez, James E Smith
"A Static Power Model for Architects"
     Jeffrey A Butts, Guri Sohi
"A Framework for Dynamic Energy Efficiency and Temperature Management"
     Wei Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
"Dynamic Zero Compression for Cache Energy Reduction"
     Luis Villa, Zhang Michael, Krste Asanovic

4:00-6:00pm, Tuesday Dec. 12, Memory Hierarchy II
Session Chair: Mike Smith -  Harvard University

"Register Integration: A Simple and Efficient Implementation of Squash 
Re-Use"
     Amir Roth, Gurindar S Sohi
"The Store-Load Address Table and Speculative Register Promotion" 
     Matthew A Postiff, David A Greene, Trevor N Mudge
"Memory Hierarchy Reconfiguration For Energy and Performance In 
General-Purpose Processor Architectures"
     Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, 
     Sandhya Dwarkadas
"Frequent Value Compression in Data Caches"
     Jun Yang, Youtao Zhang, Rajiv Gupta

8:00-10:00am, Wednesday Dec. 13, Dynamic Translation and 
Multithreading
Session Chair: Kemal Ebcioglu -  IBM

"A Study of Slipstream Processors"
     Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg
"Relational Profiling: Enabling Thread Level Parallelism in Virtual 
Machines"
     Timothy H Heil, James E Smith
"Calpa: A Tool for Automating Selective Dynamic Compilation"
     Markus U Mock, Craig Chambers, Susan J Eggers
"Increasing the Size of Atomic Instruction Blocks by using Control 
Flow Assertions"
     Sanjay J Patel, Tony Tung, Satarupa Bose, Matthew Crum

10:30-12:30am, Wednesday Dec. 13, Superscalar Architecture
Session Chair: Bob Colwell -  Intel

"Reducing Wire Delay Penalty through Value Prediction"
     Joan-Manuel Parcerisa, Antonio Gonz�lez
"Compiler Controlled Value Prediction using Branch Predictor Based 
Confidence"
     Eric Larson, Todd Austin
"Instruction Distribution Heuristics for Quad-Clustered, Dynamically-
Scheduled"
     Superscalar Processors, Amirali Baniasadi, Andreas Moshovos
"Performance Improvement with Circuit-Level Speculation"
     Tong Liu, Shih-Lien Lu


**************************************************************
ACM SIGMICRO new membership offered at half-price to MICRO-33
registrants, free for students.

About ACM SIGMICRO

The ACM Special Interest Group on Microrarchitectural Research, 
SIGMICRO [http://www.acm.org/sigmicro], specializes in computer 
microarchitecture, and especially in features permitting instruction-
level parallelism and their related implications on compiler design. 
For the past 33 years, the annual MICRO conference (co-sponsored by 
SIGMICRO) has been a key forum for presenting major breakthroughs in 
computing architecture, and has established itself as the premier 
conference on instruction level parallelism. The SIGMICRO newsletter 
publishes once a year as the conference proceedings and is included as 
a benefit of membership in the SIG (i.e. SIGMICRO members get an extra 
copy of the MICRO proceedings in the mail).

ACM SIGMICRO is the right professional organization to belong to, if 
you are a microarchitect, microprogrammer, advanced compiler designer, 
or a researcher/developer of superscalar, pipelined, or fine-grain 
parallel computer architectures, or if you are interested in learning 
more about such microarchitecture topics.


Special new SIGMICRO membership offer to MICRO-33 registrants

ACM SIGMICRO membership fees are normally $21/year for non-students 
who already are ACM members, and $8/year for students (ACM membership
is not required for students). However, for registrants of MICRO-33,
we are making the following special offer, to those who are not already
members of SIGMICRO and wish to become new members:

o If you are not a student and are already an ACM member: SIGMICRO
membership is available to you at about half price ($10), for the 
first year.

o If you are a student, you can become a SIGMICRO member for free for 
the first year-- this offer is available even if you are not an ACM 
member.

We are looking forward to seeing you as part of the ACM SIGMICRO 
community.