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Candidate: Hari Cadambi
Committee: Prof. Seth C Goldstein (Advisor)
           Prof. Don Thomas
           Prof. Herman Schmit
           Randy Harr (Synopsys, Inc.)

Title:     Static Profile Driven Optimization for Digital Circuits
Time:      2pm, Friday, Dec 1, 2000
Place:     Hamerschlag Hall 1112

Abstract:
Optimization of netlists subject to area, delay or resource
constraints is a general and common problem used in almost every stage
of CAD tools. Most forms of this problem have been proven to be
NP-complete. Instead of taking a global approach to optimize a
netlist, this thesis suggests using static hardware profiling to
identify important sub-circuits, which may then be given priority by
the tools or by human designers. Such profiling helps focus
optimization efforts on the portions of the netlist that have the
greatest impact on the final result.

A static hardware profiling tool that can rapidly extract hot-spots
from hardware descriptions has been built. Results from using this
tool to help improve the performance of a reconfigurable hardware
compiler, an ASIC technology mapper and an FPGA compiler will be
shown.