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Toward a virtual machine for hardware/software codesign

JoAnn Paul
Visiting Assistant Professor of ECE
Seminar:  Wednesday, March 22, 2000
10:30 a.m.
HH 1112

Abstract:

The design of complex computation systems ranging from cell phones to
complete vehicle-level electronics presents challenges when increases in
demand for functionality, performance, minimal design time, maintenance
and configurability are considered together.  Digital computation is
characterized by behavioral modeling to two fundamentally different
virtual machines, or scheduling paradigms, commonly known as hardware
and software. The software domain has been described as non-timed,
interleaved, configurable, dynamic, data-intensive, unbounded, and
resource-independent. The hardware domain has been described as timed,
structural, physical, dataflow, synchronous reactive, and
resource-based. Previous hardware-software codesign approaches do not
fully represent both of these domains in arbitrary system views from
highly abstract to physical implementation. Instead, they have attempted
to extend existing hardware or software virtual machines so that the
other domain's behavior
can be modeled for a given system view.

In the Center for Electronic Design Automation at Carnegie Mellon
University we are currently investigating strategies for uniting
hardware and software models of computation as merged design time and
run time scheduling.  Design time scheduling is traditionally associated
with Computer Aided Design, while run time scheduling is traditionally
associated with Computer Science or Real Time Embedded Computing.  A
novel system partitioning strategy based upon clock and bus domains is
discussed which provides the basis for a Codesign Virtual Machine (CVM).
 A novel scheduling strategy called frequency interleaving which unites
hardware and software models of computation as shared memory clock
domains is discussed in support of CVM.  Also discussed is a specific
architectural memory device and design environment called "Co-RAM" which
is a product of merged run-time and design time interleaving as applied
to a single software program.  Co-RAM allows for physically interleaved
combinational functions to be mapped to conventional memory space. 

 Bio:

Dr. JoAnn M. Paul received the Ph.D. in Electrical Engineering in 1994
from the University of Pittsburgh where she developed a novel scalable
pipelined parallel architecture with minimal latency and maximum
throughput for computation of L-U Factorization datasets.  She received
her M.S.E.C.E. from Carnegie Mellon in 1988 and her B.S.E.E (summa cum
laude) from the University of Pittsburgh in 1983. Prior to re-entering
graduate school, she was an Engineer in large and small industrial
organizations where she designed and developed software for debug
kernels, Ada runtimes, and object-oriented device drivers and software
and hardware for safety-critical protection, control, and monitoring
systems.  She is currently doing research in hardware/software codesign
and teaching at Carnegie Mellon University where she is a Visiting
Assistant Professor.  She is a Licensed Professional Engineer in the
Commonwealth of PA.