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General-Purpose Architectures for Media Processing Applications

Parthasarathy Ranganathan
Rice University

Thursday, March 23, 2000
Wean Hall 4623
10 a.m.
Abstract

Workloads on general-purpose computing systems have changed dramatically
over the past few years, with greater emphasis on applications such as
databases, media processing, networking, and communications. Several of
these workloads require orders-of-magnitude higher computing performance
than what is available in current systems. However, until recently, most
high performance computing studies have primarily focused on scientific
and engineering workloads, potentially leading to design decisions not
suitable for emerging workloads. Our work has been the first to use
detailed simulation to study several emerging workloads on
state-of-the-art general-purpose systems. In this talk, I will discuss
some of my recent work on understanding and improving the performance of
media processing workloads on general-purpose architectures.

An analysis of the effectiveness of state-of-the-art features
(techniques to extract instruction-level parallelism, media
instruction-set extensions, software prefetching, and large caches)
identifies two key trends: (1) media workloads on current
general-purpose systems are primarily compute-bound and (2) current
trends towards devoting a large fraction of on-chip transistors (up to
80%) for caches can often be ineffective for media workloads. In
response to these results, I will discuss a new cache organization,
called a reconfigurable cache, that allows the on-chip cache transistors
to be dynamically divided into partitions that can be used for other
processor activities (e.g., instruction memoization,
application-controlled memory, and prefetching buffers). Our design of
the reconfigurable cache requires very few modifications to existing
caches and has small impact on cache access times. I will discuss how,
for media applications, reconfigurable caches can be effectively used
for instruction memoization to reuse memory for computation.

Bio:

Parthasarathy Ranganathan received his B.Tech degree from the Indian
Institute of Technology, Madras in 1994, and his M.S. degree from Rice
University in 1997. He is currently a doctoral candidate at the
Department of Electrical and Computer Engineering at Rice University.
His research interests are in high-performance computer architecture,
parallel computing, and performance evaluation, with specific focus on
architectures for emerging applications and techniques to use
instruction-level parallelism. He is a primary developer and maintainer
of the publicly distributed Rice Simulator for ILP Multiprocessors
(RSIM) and a recipient of the Lodieska Stockbridge Vaughan fellowship.
He is also the secretary of the IIT Madras alumni association overseeing
all North American activities. More details can be found at
www.ece.rice.edu/~parthas