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Compiler-directed Synthesis of Hardware Accelerators

Scott A. Mahlke
March 27, 2000
10:00
Hamerschlag Hall 1112

Abstract:

An ever larger variety of embedded ASICs is being designed and deployed
to satisfy the explosively growing market for new electronic devices. 
Many of these devices handle demanding multi-media computations.  In
many such ASICs, specialized nonprogrammable hardware accelerators
(NPAs) are used for parts of the application that would run too slowly
if implemented in software on a programmable processor.  Rapid, low-cost
design, low production cost, and high performance are all important in
NPA design.  In order to reduce the design time and design cost,
automated design of NPAs from high-level specifications is becoming
increasingly important.  A principal goal of the HP Labs
Program-In-Chip-Out (PICO) project is to automate the design of NPAs.

One of the critical factors in this design process is the width of the
data processed by the application.  The width of the data directly
controls the width of the necessary hardware components and thus the
cost of the NPA.  In most multi-media applications, full 32-bit integer
data is rarely required. Therefore, the cost of the hardware can be
substantially reduced by detecting narrow computations and synthesizing
narrow hardware components.  The PICO synthesis system employs an
automatic bitwidth analysis system to derive the width for each
variable, temporary, and operator within an application.  This
information is then used to drive hardware synthesis to create
width-conscious designs of NPAs.  In this talk, I will first present an
overview of the PICO project and the NPA synthesis system that has been
developed.  Second, the bitwidth analysis system is examined in more
depth.  Our approach and some experiments demonstrating the
effectiveness of the analysis are presented.

Speaker Biography:

Scott Mahlke is a member of the Compiler and Architecture Research group
at HP Laboratories  Since joining HP in 1994, he has worked on the
development of high-performance computing technology.  The primary focus
of his current work is automated design of application-specific embedded
processors and hardware accelerators.  Previously, he focused on
architecture and compilation technology for Explicitly Parallel
Instruction Computing (EPIC) style architectures, including predicated
execution, speculative execution, and branch prediction.  This work
contributed to the development of the Elcor and Impact compilers.  Scott
received his Ph.D. degree from the University
of Illinois.