🚀 go-pugleaf

Exploiting Instruction-Level Parallelism for Memory System Performance
Vijay S. Pai
Rice University
Thursday, March 30, 2000
10:00 a.m.
Wean Hall 4623

Abstract:

Current microprocessors improve performance by exploiting
instruction-level parallelism (ILP). ILP hardware techniques such as
multiple instruction issue, out-of-order (dynamic) issue, and
non-blocking reads can accelerate both computation and data memory
references. Since computation speeds have been improving faster than
data memory access times, memory system performance is quickly becoming
the primary obstacle to achieving high performance. (This trend is
sometimes called the "memory wall".) My work focuses on exploiting ILP
techniques to improve memory system performance. In
this talk, I present both an analysis of ILP memory system performance
and optimizations developed using the insights of this analysis.

I show that ILP hardware techniques, used in isolation, are often
unsuccessful at improving memory system performance, because they fail
to extract parallelism among data reads that miss in the processor's
caches. Software prefetching provides some improvement by initiating
data read misses earlier, but also suffers from limitations caused by
exposed startup latencies, excessive fetch-ahead distances, and
references that are hard to prefetch.

I use the above insights to develop compile-time software
transformations that improve memory system parallelism and performance.
These transformations improve the effectiveness of ILP hardware,
reducing exposed latency by over 80% for a latency-detection
microbenchmark and reducing execution time an average of 25% for 7
applications studied. These transformations also address key limitations
in current software prefetching algorithms, reducing execution time an
average of 24% relative to prefetching alone.

Bio:

Vijay S. Pai received the B.S.E.E. degree in 1994 and the M.S. degree in
1997, both from Rice University. He is currently completing his Ph.D.
degree at the Department of Electrical and Computer Engineering, Rice
University.  His research interests include computer architecture,
optimizing compilers, parallel computing, and performance evaluation. 
He is also a primary developer and maintainer of the publicly-available
Rice Simulator for ILP Multiprocessors (RSIM).  Vijay is a member of the
Eta Kappa Nu, Phi Beta Kappa, and Tau Beta Pi honorary societies, and
his graduate education has been
partly supported by a Hertz Fellowship.  In his spare time, he is a
recreational runner and drummer, with a history of 2 bubblegum-pop bands
and 1 guitar-rock band.