🚀 go-pugleaf

Intelligent Distributed Shared Memory:
The Future of Scalable Server Architectures
Babak Falsafi
Assistant Professor, Purdue University
Monday, April 3, 2000
HH 1112
11:00
Abstract

Distributed shared memory (DSM) is emerging as the architecture of
choice for building large-scale multiprocessor servers. DSMs remove the
bandwidth and size limitations of a single memory module and provide a
shared-memory programming interface over memory that is distributed
among the processors. Tuning applications for performance on DSMs,
however, can often be difficult due to the non-uniform nature of memory;
in DSMs, remote memory accesses inherently take several times longer
than local memory accesses. In this talk I will present an overview of
the Purdue Impetus project, focusing on the design of intelligent DSMs
that appear (to software) to have a uniform memory architecture, thus
enhancing programmability and software portability. In these DSMs, the
memory system transparently-rather than involving the application
software--hides and/or tolerates the remote memory latency, reducing the
performance gap between remote and  local memory.

In the first half of the talk, I will present results that put to rest
the long and heated debate in the architecture community on whether
multiprocessors must support sophisticated memory programming
interfaces--better known as memory consistency models--to achieve high
performance. Modern processors support a variety of memory models to
allow software to indicate when it is safe for hardware to overlap
multiple remote memory accesses and tolerate latency.  I identify the
key mechanisms that allow memory to provide the simple and intuitive
uniprocessor programming model while achieving the performance only
possible with the most sophisticated memory models. In the second half
of the talk, I will present novel DSMs which capitalize on repetitive
memory sharing behavior in applications. By learning and predicting such
sharing behavior at runtime, these DSMs can move shared data among the
processors in advance to hide some or all of the remote access latency.

Bio:

Babak Falsafi is an Assistant Professor in the School of Electrical and
Computer Engineering at Purdue University. He received a B.S. in
Computer Sciences and a B.S. in Electrical and Computer Engineering with
highest distinctions in 1990 from SUNY at Buffalo, and a Ph.D. in
Computer Sciences in 1998 from University of Wisconsin. He is the
recipient of an NSF CAREER award in 2000 and his contributions include a
novel memory architecture, Reactive NUMA, recently incorporated in a Sun
Microsystems server. His research interests include
prediction/speculation in high-performance memory systems, power-aware
processor/memory architectures, billion-transistor single-chip
architectures, and analytic/simulation tools for computer system
performance evaluation. He is currently the principal investigator of
the Purdue Impetus project (URL: http://www.ece.purdue.edu/~impetus)
designing and evaluating intelligent memory systems. He also co-leads
the Purdue ICALP project, targeting an integrated architectural and
circuit-level approach to power management in computer systems; and the
Purdue Multiplex project, designing billion-transistor single-chip
architectures. He is
a member of IEEE and ACM.