🚀 go-pugleaf

---------------
Would you be kind enough to forward this PACT2000 conference announcement
to your IEEE Student Branch members.  I think this conference may be of
interest to some of them.  Thank you in advance for your help.  Please
feel free to contact me with any questions about the conference.

Prof. Ben Lee
PACT2000
Publicity Chair

____________________________________________________________________________

Dear Colleagues:

Please accept my sincere apologies if you receive multiple copies of this
PACT2000 Advance Program announcement. Please note that early registration
will end on September 22 at 5 PM Eastern Time. 

*************************************************************************
*									*
*                      INTERNATIONAL CONFERENCE ON                  	* 
*	       PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES    	*
*                         October 15-19, 2000                       	*
*                    Sheraton University City Hotel                 	*
*                     Philadelphia, Pennsylvania, USA               	*
*                    http://www.ece.orst.edu/~pact2000              	* 
*                           ADVANCE PROGRAM                         	*
*         Sponsored by IFIP WG 10.3, ACM SIGARCH, IEEE TCCA and TCPP,	*
*             with generous support from Intel, SGI, and IBM.		*
*                                                                   	*
*                                                                   	*
*************************************************************************
We suggest that you register and make your hotel reservations as soon as
possible to benefit from the discounted rates. A number of student travel
grants are also available, and students are encouraged to apply. Early
registration will end on September 22 at 5 PM Eastern Time.

________________________________________________________________________
Keynote speakers:
Fred Pollack (Intel): New Challenges in Microarchitecture and Compiler
Design
Mike Smith (Harvard University): Dynamic Optimization: An Online
Opportunity
Monty Denneau (IBM T.J. Watson Research Center): Blue Gene
________________________________________________________________________
Sunday, October 15: Tutorials
Tutorial 1: 	Low Power Design Methodologies: Hardware and Software Issues
		by Mary Jane Irwin (Penn State), Mahmut Kandemir (Penn State),
		and Vijaykrishnan Narayanan (Penn State)
Tutorial 2: 	An Introduction to the SGI Pro64 Compiler Infrastructure
		by Guang R. Gao (U. of Delaware), N. Amaral (U. of Alberta), 
		J. Dehnert (SGI),and  R. Towle (SGIP)


Monday, October 16 
8:30-9:15	Coffee
9:15-9:30	Welcome
		Ali Hurson, Conference Chair
9:30-10:30	Keynote Speaker
		Fred Pollack, Intel Corporation 
		New Challenges in Microarchitecture and Compiler Design
10:30-11:00	Break
11:00-12:30	Session 1: Register Allocation and Analysis
11:00-11:30	Register Queues: A New Hardware/Software Approach to Efficient 
		Software Pipelining 
		by Mikhail Smelyanski, Gary Tyson and Edward Davidson 
		(University of Michigan) 
11:30-12:00	Global Register Partitioning 
		by Jason Hiser (University of Virginia), Steve Carr and Philip 
		Sweany (Michigan Technological University) 
12:00-12:30	Region Formation Analysis with Demand-driven Inlining for 
		Region-Based Optimization 
		by Tom Way, Ben Breech and Lori Pollock (University of Delaware) 
12:30-2:00	Lunch
2:00-3:30	Session 2: Architectural Design
2:00-2:30	aSOC: A Scalable, Single-Chip Communication Architecture 
		by Jian Liang, Sriram Swaminathan, and Russell Tessier 
		(University of Massachusetts) 
2:30-3:00	Address Partitioning in DSM Clusters with Parallel Coherence 
		Controllers 
		by Ilanthiraiyan Pragaspathy and Babak Falsafi (Purdue 
		University) 
3:00-3:30	Custom Wide Counterflow Pipelines for High-Performance Embedded 
		Applications 
		by Bruce R. Childers (University of Pittsburgh) and Jack W. 
		Davidson (University of Virginia) 
3:30-4:00	Break
4:00-5:40	Session 3: Optimizations and Opportunities
4:00-4:30	A Lightweight Algorithm for Dynamic If-Conversion during 
		Dynamic Optimization 
		by Kim M. Hazelwood and Thomas M. Conte (North Carolina State 
		University) 
4:30-5:00	Exploring the Limits of Sub-word Level Parallelism 
		by Kevin Scott and Jack Davidson (University of Virginia) 
5:00-5:20	The Dynamic Trace Memoization Reuse Technique 
		by Amarildo da Costa, Felipe Franca and Eliseu Filho 
		(University of Rio de Janeiro, Brazil) 
5:20-5:40	Exploring Sub-block Value Reuse for Superscalar Processors 
		by Jian Huang (Sun Microsystems) and David Lilja (University of 
		Minnesota) 

Tuesday, October 17 
8:30-9:00	Coffee
9:00-10:00	Keynote Speaker
		Michael Smith, Harvard University 
		Dynamic Optimization: An Online Opportunity
10:00-10:30	Break
10:30-12:00	Session 4: High Performance Memory Techniques
10:30-11:00	Hiding Relaxed Memory Consistency with Compilers 
		by Jaejin Lee (Michigan State University) and David A. Padua 
		(University of Illinois at Urbana-Champaign) 
11:00-11:30	Neighborhood Prefetching on Multiprocessors Using Instruction 
		History 
		by David Koppelman (Louisiana State University) 
11:30-12:00	Characterization of Silent Stores 
		by Gordon Bell, Kevin M. Lepak and Mikko H.Lipasti (University 
		of Wisconsin) 
12:00-2:00	Lunch
2:00-3:20	Session 5: Speculation and Prediction
2:00-2:30	On Some Implementation Issues for Value Prediction on Wide-
		Issue Processors 
		by Sang-Jeong Lee (Soonchunhyang University, Korea) and
		Pen-Chung Yew (University of Minnesota) 
2:30-3:00	A Unified Compiler Framework for Control and Data Speculation 
		by Roy Dz-ching Ju (Intel Corporation), Kevin Nomura (Network 
		Applications), Uma Mahadevan and Le-Chun Wu (Hewlett-Packard 
		Company) 
3:00-3:20	Applying Data Speculation in Modulo Scheduled Loops 
		by Uma Mahadevan (Hewlett Packard Company), Kevin Nomura 
		(Network Applications), Roy Dz-ching Ju (Intel Corporation) and
 		Rick Hank (Hewlett Packard Company) 
3:20-4:00	Break
4:00-5:40	Session 6: Branch Prediction
4:00-4:30	Branch Prediction in Multi-Threaded Processors 
		by Jayanth Gummaraju and Manoj Franklin (University of 
		Maryland) 
4:30-5:00	The Effect of Code Reordering on Branch Prediction 
		by Alex Ramirez, Josep L. Larriba-Pey and Mateo Valero 
		(Universitat Politecnica de Catalunya, Spain) 
5:00-5:20	A Taxonomy of Branch Mispredictions, and Alloyed Prediction as 
		a Robust Solution to Wrong-History Mispredictions 
		by Kevin Skadron (University of Virginia), Margaret Martonosi 
		and Douglas W. Clark (Princeton University) 
5:20-5:40	Dynamic Branch Prediciton for a VLIW Processor 
		by J. Hoogerbrugge (Phillips Research Laboratories, the 
		Netherlands) 

Wednesday, October 18 
8:30-9:00	Coffee
9:00-10:00	Keynote Speaker
		Monty Denneau, IBM T.J. Watson Research Center 
		Blue Gene
10:00-10:30	Break
10:30-12:00	Session 7: Parallel Computation
10:30-11:00	Fine Grained Multithreading with Process Calculi 
		by Luis Lopes, F. Silva and V. Vasconcelos (University of 
		Porto, Portugal) 
11:00-11:30	Data Relation Vectors: A New Abstraction for Data Optimizations 
		by Mahmut Kandemir (Pennsylvania State University) and 
		J. Ramanujam (Louisiana State University) 
11:30-12:00	Combined Selection of Tile Sizes and Unroll Factors Using 
		Iterative Compilation 
		by T. Kisuki and P.M.W. Knijnenburg (Leiden University, The 
		Netherlands) and M.F.P. O'Boyle (Edinburgh University, UK) 
12:00-1:30	Lunch
1:30-2:50	Session 8: Applications
1:30-2:00	Faster FFTs via Architecture-Cognizance 
		by Kang Su Gatlin and Larry Carter (University of California 
		San Diego) 
2:00-2:30	Hybrid Parallel Circuit Simulation Approaches 
		by Edwin Naroska (University of Dortmund), Rung-Ji Shang and 
		Feipei Lai (National Taiwan University), and Uwe
		Schwiegelshohn (University of Dortmund) 
2:30-2:50	Multithreaded programming of PC clusters 
		by Martin Schulz (Technische Universitat Munchen) 
2:50-3:15	Break
3:15-4:35	Session 9: Instruction Scheduling
3:15-3:45	A Fast Algorithm for Scheduling Instructions with Deadline 
		Constraints on RISC Processors 
		by Hui Wu, Joxan Jaffar and R. Yap (National University of 
		Singapore) 
3:45-4:15	Instruction Scheduling for Clustered VLIW DSPs 
		by Rainer Leupers (University of Dortmund) 
4:15-4:35	Efficient Backtracking Instruction Schedulers 
		by Santosh G. Abraham (Hewlett-Packard Laboratories), Waleed M. 
		Meleis and Ivan D. Baev (Northeastern University)

Thursday, October 19: Workshops
Workshop 1: 	Compilers and Operating Systems for Low Power
		Co-Chairs: Mahmut Kandemir (Penn State) and J. Ramanujam 
		(Louisiana State University)
Workshop 2: 	Memory Access Decoupling for Superscalar and Multiple
		Issue Architectures (MEDEA)
		Co-Chairs: Roberto Giorgi (University of Siena, Italy),
		Cosimo Antonio Prete (University of Pisa, Italy), and
		Jelica Protic (University of Belgrade, YU)
Workshop 3: 	Binary Translation (WBT-2000)
		Co-Chairs: Erik Altman (IBM T.J. Watson Research Center)
		and David Kaeli (Northeastern University)
Workshop 4: 	Ubiquitous Computing  
		Chair: Djamshid Tavangarian (University of Rostock)
______________________________________________________________________________
Organizing Committee:

General Chair		Ali R. Hurson, Penn State University

Program Committee	Mary Lou Soffa, University of Pittsburgh (Chair)
			Nader Bagherzadeh, UCI
			Luc Bouge, LIP, ENS Lyon, France
			Bruce Childers, University of Pittsburgh
			Jong-Deok Choi, IBM T.J. Watson Research Center
			Michel Cosnard, LORIA-INRIA, France
			Jack Davidson, University of Virginia
			Jim Dehnert, SGI
			Evelyn Duesterwald, Hewlett Packard Labs
			Kemal Ebcioglu, IBM T.J. Watson Research Center
			Paraskevas Evripidou, University of Cyprus
			Jesse Fang, Intel Corp. 
			Jeanne Ferrante, UCSD
			Akira Fukuda, Nara Institute of Science and
				Technology
			Guang Gao, University of Delaware
			Jean-Luc Gaudiot, USC
			Mary Hall, University of Southern California, ISI
			Ali Hurson, Penn State University
			David Kaeli, Northeastern University
			Artur Klauser, Compaq Computer Corporation
			Mikko Lipasti, University of Wisconsin
			Josep Lluis Larriba-Pey, Universitat Politecnica
				de Catalunya
			Scott Mahlke, HP Laboratories
			Sally McKee, University of Utah
			Avi Mendelson, Intel, Israel
			David O'Hallaron, CMU
			Soner Onder, Michigan Technological University
			Lori Pollock, University of Delaware
			Gabby Silberman, IBM
			Kevin Skadron, University of Virginia
			Jim Smith, University of Wisconsin
			J. Ramanujam, Louisiana State University
			Josep Torrellas, University of Illinois at
				Urbana-Champaign 
			Theo Ungerer, University of Karlsruhe, Germany
			Andrew Wendelborn, University of Adelaide 

Steering Committee	Kemal Ebcioglu, IBM (Chair)
			Michel Cosnard, Loria, France
			Jean-Luc Gaudiot, USC
			Nader Bagherzadeh, UC Irvine
			Paraskevas Evripidou, University of Cyprus
			Gabby Silberman, IBM
			Ulrich Finger, ENST, France
			Guang Gao, University of Delaware

Publicity Chair		Ben Lee, Oregon State University

Regional 
Publicity Co-Chairs	Far East and Asia: Albert Zomaya, University of
			Western Australia
			Europe: Mateo Valero, Universitat Politecnica de
                        Catalunya

Prog. Comm. Web Master	Bruce Childers, University of Pittsburgh

Local 
Arrangements Chair	Constantine Katsinis, Drexel University

Publication Chair	Guang Gao, University of Delaware

Finance Chair		Lynn Choi, University of California, Irvine

Tutorial Chair		John Hannan, Pennsylvania State University

Workshops Chair		Krishna Kavi, University of Alabama, Huntsville
___________________________________________________________________________

Thank you very much for your time in reading this announcement. I would
appreciate if you could pass it on to other colleagues who may be
interested. Please feel free to contact me with any questions.

Prof. Ben Lee
Oregon State University
PACT 2000 Publicity Chair
benl@ece.orst.edu