🚀 go-pugleaf

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`timescale 1ns / 1ns
module control (rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel,opcode
, zero, clk, rst);
`define output1 {rd,wr,ld_ir,ld_acc,ld_pc,inc_pc,halt,data_e,sel}
  output       rd, wr, ld_ir, ld_acc, ld_pc, inc_pc, halt, data_e, sel;  
  input [2:0]  opcode;
  input        zero, clk, rst;
  reg rd,wr,ld_ir,ld_acc, ld_pc, inc_pc, halt, data_e, sel;
  reg state=1'd0;
  
  
  task t1;
  input [2:0]opcode1;
  output[8:0]output12;
  begin
  case(opcode1)
  3'b010,3'b011,3'b100,3'b101 :output12=9'b100000000;
  3'b000,3'b001,3'b110,3'b111 :output12=9'b000000000;
  endcase
  end
  endtask
  task t2;
  input[2:0]opcode1; 
  input zero1;
  output [8:0]output12;
  begin
  if(zero1==1) output12=9'b000001010;
  case(opcode1)
  3'b010,3'b011,3'b100,3'b101 :output12=9'b100000000;
  3'b000,3'b001,3'b110:output12=9'b000000010;
  3'b111:output12=9'b000010010;
  endcase
  end
  endtask
  task t3;
  input [2:0] opcode1;
  input zero1;
  output [8:0]output12;
  begin
  if(zero1==1) output12=9'b000001010;
  case(opcode1)
  3'b010,3'b011,3'b100,3'b101 :output12=9'b100100000;
  3'b000,3'b001:output12=9'b000000010;
  3'b110: output12=9'b010000010;
  3'b111: output12=9'b000011010;
  endcase
  end
  endtask 
  
  
  
  
 always@(clk)
 case(state)
      1'd0: 
      begin `output1=9'b000000001;state=state+1;
      end
      1'd1: 
      begin `output1=9'b100000001;state=state+1;
      end
      1'd2: 
      begin `output1=9'b101000001;state=state+1;
      end
      1'd3: 
      begin 
      `output1=9'b101000001;state=state+1;
      end
      1'd4: 
      if(opcode==3'b000) begin `output1=9'b000001100;state=state+1;end
      else 
      begin  `output1=9'b000001000;state=state+1;state=state+1;
      end
      1'd5: begin state=state+1;t1(opcode,`output1);end
      1'd6: begin state=state+1;t2(opcode,zero,`output1);end
      1'd7: begin state=state+1;t3(opcode,zero,`output1);end
endcase

always@(rst)

if(rst==0)   
begin `output1=9'b000000000;
state=1'd0;
end
endmodule

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