Article View: comp.arch.storage
Article #18Re: IPI-2 questions
From: Adams
Date: Wed, 05 Aug 1992 01:35
Date: Wed, 05 Aug 1992 01:35
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In article <1992Jul27.232740.3237@telematics.com> ted@telematics.com (Ted Goldblatt) writes: > not: SCI is in no way a replacement for IPI or any other I/O > bus. SCI is a processor/memory interconnect (i.e., if it > replaces anything, it replaces the system's _memory_ bus) > intended for large to very large coherent shared memory > multiprocessors. While I'm sure it can (and will) be used > for other things, I don't think that an I/O bus replacement > is one of them. Right and wrong. SCI offers a 64-bit address space (4*1024*1024*1024*4GByte), but no one makes any assumption about implementation of huge memory. Might it be possiple, that a cpu will see a huge, flat memory area and won't care about blocks and tracks in the future? Perhaps, dedicated I/O busses will be out then as "memory servers" do not even know about them anymore.... Perhaps you might be forced to maintain coherency even on mass storage devices? Common controller interface need not be approbriate ... Not yet sure about future I/O busses ... adams
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Newsgroups: comp.arch.storage Path: arc1-ca.pugleaf.net!sparky!uunet!math.fu-berlin.de!news.th-darmstadt.de!adams From: adams@pdv2.fmr.maschinenbau.th-darmstadt.de (Adams) Subject: Re: IPI-2 questions Sender: news@infoserver.th-darmstadt.de (The Usenet-News System) Message-ID: <ADAMS.92Aug5013521@PDV2.pdv2.fmr.maschinenbau.th-darmstadt.de> In-Reply-To: ted@telematics.com's message of 27 Jul 92 23: 27:40 GMT Date: Wed, 5 Aug 1992 01:35:21 GMT References: <ADAMS.92Jul16014945@PDV2.pdv2.fmr.maschinenbau.th-darmstadt.de> <BrH2sz.5qM@csn.org> <ADAMS.92Jul16125743@PDV2.pdv2.fmr.maschinenbau.th-darmstadt.de> <1992Jul27.232740.3237@telematics.com> Nntp-Posting-Host: pdv2.fmr.maschinenbau.th-darmstadt.de Organization: TH-Darmstadt Lines: 24