🚀 go-pugleaf

Some of you are probably already familiar with MOSIS, but since the
discussion seems to be headed that way, I'll put in a plug for us. If
you're hooked in to MOSIS, you can design a chip (usually in scalable
CMOS design rules which we can provide you a copy of), submit it to be
fabbed (preferably by email), and in usually 8-12 weeks (depending on
which process, glitches we hit, etc.) you get back some number of
copies of your chip.

If you're at a university with VLSI design classes, the odds are good
you're already set up with us. Commercial people can get in, too. Call
(213)822-1511 and ask for MOSIS. Tell whoever answers that you want to
find out about fabbing through us -- they should know enough to get
you started on the paperwork.

Price? I don't know, since I'm not connected with production stuff (I
do unrelated programming & have never been familiar with any of that),
but I think the bottom is around $500 for four copies of a tiny chip,
which, I seem to recall somebody telling me, is good for about 10K
gates, depending on your design style. That's in 2 micron CMOS. We
also support 1.6, and maybe 1.2. You can submit designs of virtually
any size and request virtually any number of parts, but it'll cost you
more.

As for "automatic" design, my boss wrote a book called _VLSI: Silicon
Compilation and the Art of Automatic Microchip Design_, Ron Ayres,
Prentice-Hall, 1983. He can take logic equations and generate layout
(though I think it's pretty inefficient, it does work). This is
separate from MOSIS. There is (or used to be) a company called Silicon
Compilers which used his stuff. There are also techniques for taking
logic circuit designs and producing layout, but I'm completely
unfamiliar with them. I have no doubt that this area is being explored
in the research community, though I haven't a clue where you'd find
out about it.

That's virtually everything I know about both topics, but I could
probably refer you to people who know more if yo'ure interested.

			--Rod