Article View: comp.arch
Article #10458Re: Compilers and efficiency
From: Michael Meissner
Date: Thu, 25 Apr 1991 17:45
Date: Thu, 25 Apr 1991 17:45
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1352 bytes
In article <4082@batman.moravian.EDU> halkoD@batman.moravian.EDU (David Halko) writes: | I wonder if RISC architecture is all what it is cracked up to be. I work on | a SUN SS1, and it is not all that much faster than a 3/60. Quite often, I | use the 3/60's we have instead. From your posting, I would guess that you use a lot of integer multiplies (non-constant in particular). The initial Sparc hardware does not have an integer multiply or divide instruction. It has a multiply step instruction (not sure about divide) to give a partial answer. -- Michael Meissner email: meissner@osf.org phone: 617-621-8861 Open Software Foundation, 11 Cambridge Center, Cambridge, MA, 02142 Considering the flames and intolerance, shouldn't USENET be spelled ABUSENET?
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uwm.edu!spool.mu.edu!snorkelwacker.mit.edu!paperboy!meissner From: meissner@osf.org (Michael Meissner) Newsgroups: comp.arch Subject: Re: Compilers and efficiency Message-ID: <MEISSNER.91Apr25134521@curley.osf.org> Date: 25 Apr 91 17:45:21 GMT References: <27fa3350.6bc2@petunia.CalPoly.EDU> <9782@mentor.cc.purdue.edu> <4082@batman.moravian.EDU> Sender: news@OSF.ORG Organization: Open Software Foundation Lines: 17 In-reply-to: halkoD@batman.moravian.EDU's message of 23 Apr 91 15:31:37 GMT