🚀 go-pugleaf

In article <12785@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes:
>In particular, most daydreams have been about casting a single
>specific algorithm to hardware. If a chemical-bonding problem is
>going to take days to grind, why not make an overnight chip, that has
>parallel execution units, one for each aspect of that particular
>molecule?  And (more down to earth, or anyway MOSIS) why shouldn't an
>encryption chip have a 500-bit-wide ALU?

There's also a middle ground -- (speaking of 500-bit wide ALUs) check
out Computer Architecture News of March 1991, "Hardware Speedups in
Long Integer Multiplication", by Shand, Bertin, Vuillemin.  They used
"Programmable Active Memory" to implement (among other things) a 32 by
512 bit multiplier, and 200Kbit/sec RSA en/decryption (512-bit keys).

A PAM consists of a 5 by 5 array of LCA (Xilinx PGA data book) chips,
plus 4 megabits of static RAM.  Several of these were used to
implement fast RSA.  One point worth noting is that (as I understand
it) the PAM is reconfigured for each key -- the (automatic)
"compilation" to do this takes about 30 minutes (downloading to PAM is
much faster).

Note the benefits -- extreme customization allows high performance,
programmability allows turnaround in under one hour, and you can do
something else with the hardware when you are done with that problem.

Read the paper.  It's very interesting.

David Chase
Sun