🚀 go-pugleaf

In article <TH_A6-F@xds13.ferranti.com>, peter@ficc.ferranti.com (peter da silva) writes:
> In article <1991Apr26.073829.4625@kithrup.COM>, sef@kithrup.COM (Sean Eric Fagan) writes:
> > Or don't you realize you can only access one memory location at a time?
> > (Well, not completely true, but true enough.)
> 
> Ah, the old Von Neumann botleneck. Time to apply RISC design techniques to
> memory subsystems. How about multiported memory, or even banked memory?
> Multiple data and address busses? Who knows, but memory subsystems are the
> current bottleneck and something's gotta give.

The CYBER 205/ETA 10 is a vector pipeline machine, with the most versatile
vector architecture I know of.  With slight modification, it would be able
to handle in a single instruction vectors of arbitrary length, and one does
not have to worry about alignment of vectors in vector registers.  At any
rate, each pipe manages 2 inputs and one output per cycle.  (Pipes are 
splitting the vector, so there is no memory conflict.)  There are also other
instruction in which 2 words at a time are used, and this is normal.
-- 
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907-1399
Phone: (317)494-6054
hrubin@l.cc.purdue.edu (Internet, bitnet)   {purdue,pur-ee}!l.cc!hrubin(UUCP)