🚀 go-pugleaf

In article <1991May2.015410.1470@news.arc.nasa.gov> lamaster@pioneer.arc.nasa.gov (Hugh LaMaster) writes:

>The fact that 16 AR's are not enough, is an amusing criticism.  True, but
>what superscalar machine of today can map 16*64KW*8Bytes/Word  = 8 MegaBytes
>in its TLB?  The ETA-10 had even bigger large pages...

	The Ardent (now Stardent) Titan P3 maps 256 MBytes in it vector tlb.
>
>PROPHECY:  One of these days, a single-chip microprocessor will have vector
>instructions, and then the advantages and disadvantages of various
>architectural decisions will be discovered all over again.

	The tradeoff to be decided is when the 1 million gates of a vector
unit aren't better spent on more D cache.  I think that once you get 32 K
or perhaps 64 K D cache on chip, then it's worth it to spend your next million
gates on a vector unit.  I think you will see such a chip in 1994. (But then, 
what do I know?)

>
>  Hugh LaMaster, M/S 233-9,  UUCP:                ames!lamaster
>  NASA Ames Research Center  Internet:            lamaster@ames.arc.nasa.gov
>  Moffett Field, CA 94035    With Good Mailer:    lamaster@george.arc.nasa.gov 
>  Phone:  415/604-6117                            #include <std.disclaimer> 


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