🚀 go-pugleaf

In article  (Dik T. Winter) writes:
>In article (Gord Deinstadt) writes:
> > In a pipelined machine, would it not be more efficient to just deactivate
> > a couple of instructions rather than go through the pain of a forward
> > branch?  In other words just keep grinding forward, but inhibiting
> > execution for a specified number of cycles, rather than trying to
> > change course.
>
>Interestingly, this is what a very old (and not very RISC) machine did.
>I am talking about the Electrologica X8 of 60s vintage.  It had a single
>condition bit.  (Nearly) Every instruction had a 2 bit field that encoded
>one of the following:
> [[[Stuff deleted]]]

Actually, at least one of the RISC architecture on the market does that.
That is the Arcon RISC chip.  I think that the chip is currently fab by
VLSI Technology and it is also available as a standard cell.

The Arcon RISC chip has one (or two??) conditional execution bit in each
instruction and depends on the condition set by previous instructions, the
instruction may behaves just like a NOP.  For small branchs, it is a very
good idea.  However, I don't think that this will work with super-scalar
architecture at all (without pain).

-- Mike
   my@berlioz.nsc.com