Re: New Moto chips (was Will NeXT survive?)

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Article #10635

#10635

From: Wm E Davidsen Jr
Date: Mon, 06 May 1991 13:15

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In article <14720@encore.Encore.COM> jcallen@encore.Com (Jerry Callen) writes:

| - a 68040 with the MMU and FPU disabled
| - a 68030 with the MMU disabled

  Following in Intel's footsteps, taking something functional and
reducing functionality to boost the profit margin and hurt competition.
There's a nice technical term for chips with functions disabled by bean
counters: capon. 
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
        "Most of the VAX instructions are in microcode,
         but halt and no-op are in hardware for efficiency"

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<11399@uwm.edu> <JH_ABJF@xds13.ferranti.com> <1991Apr29.144421.19819@oakhill.sps.mot.com> <+=+A+N6@xds13.ferranti.com> <3397@crdos1.crd.ge.COM> <14720@encore.Encore.COM>

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: New Moto chips (was Will NeXT survive?)
Message-ID: <3403@crdos1.crd.ge.COM>
Date: 6 May 91 13:15:28 GMT
References: <11399@uwm.edu> <JH_ABJF@xds13.ferranti.com> <1991Apr29.144421.19819@oakhill.sps.mot.com> <+=+A+N6@xds13.ferranti.com> <3397@crdos1.crd.ge.COM> <14720@encore.Encore.COM>
Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen)
Organization: GE Corp R&D Center, Schenectady NY
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