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Article #10658

Re: Vector vs Cache/Superscalar

#10658
From: Rowan Hughes
Date: Tue, 07 May 1991 04:08
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In <1991May6.055943.6234@midway.uchicago.edu> rtp1@quads.uchicago.edu (raymond thomas pierrehumbert) writes:
>I wonder how the Fujitsu handles the recursion.  For long enough
>vectors to make it worthwhile, there is a pretty well known hack
>to make sum-reduction vectorizable (split the vector in two,
>do a vector add, split again, etc.).  Works for dot products as
>well, of course.  The RISC architectures can handle a much
>more general kind of recursion.

The sum-reduction has been on vector machines for many years. The
recurrsion I meant was  A(I)=A(I-1) + ... in general, when reordering
is just not possible. The theoretical solution has also been around for
several years, but Fijitsu appears to be the first vendor to have used it.
See Willie Schonauer's book for the theory.
"Scientific Computing on Vector Computers"
Willie Schonauer, Elsevier Sci Pub  1987, ISBN 0444702881
Although a little dated now, it gives an excellent review of several
vector architectures, and algorithms.

-- 
Rowan Hughes                                James Cook University
Marine Modelling Unit                       Townsville, Australia.
Dept. Civil and Systems Engineering         csrdh@marlin.jcu.edu.au
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References: <1991May4.031835.7979@midway.uchicago.edu> <MCCALPIN.91May5075614@pereland.cms.udel.edu> <1991May6.035310.26794@marlin.jcu.edu.au> <1991May6.055943.6234@midway.uchicago.edu>

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From: csrdh@marlin.jcu.edu.au (Rowan Hughes)
Newsgroups: comp.arch
Subject: Re: Vector vs Cache/Superscalar
Message-ID: <1991May7.040852.3245@marlin.jcu.edu.au>
Date: 7 May 91 04:08:52 GMT
References: <1991May4.031835.7979@midway.uchicago.edu> <MCCALPIN.91May5075614@pereland.cms.udel.edu> <1991May6.035310.26794@marlin.jcu.edu.au> <1991May6.055943.6234@midway.uchicago.edu>
Organization: James Cook University
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