Re: Vector vs Cache/Superscalar

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Article #10709

#10709

From: Sadun Anik
Date: Wed, 08 May 1991 08:49

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In article <GLEW.91May7175310@pdx007.intel.com> glew@pdx007.intel.com (Andy Glew) writes:

      [ stuff deleted ]   
   
       So: why not combine vector memory access instructions that convey
   access pattern, with scalar computational operations?


   I thought Davidson's SMA architecture could do this. If I remember
correctly, a decoupled memory access unit could handle vector access and other
data structures. I don't know how much of the original SMA concepts are
implemented in ZS1 processor.

--
Sadun Anik, U of Illinois at Urbana-Champaign
e-mail: anik@crhc.uiuc.edu

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From: anik@crhc.uiuc.edu (Sadun Anik)
Newsgroups: comp.arch
Subject: Re: Vector vs Cache/Superscalar
Message-ID: <ANIK.91May8034933@lyra.crhc.uiuc.edu>
Date: 8 May 91 08:49:33 GMT
References: <1991May4.031835.7979@midway.uchicago.edu>
 <1991May6.035310.26794@marlin.jcu.edu.au> <11921@mentor.cc.purdue.edu>
 <GLEW.91May7175310@pdx007.intel.com>
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Organization: Center for Reliable and High-Performance Computing
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In-Reply-To: glew@pdx007.intel.com's message of 7 May 91 16:53:10 GMT

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