🚀 go-pugleaf

Andrew Glew, of Intel, writes
>    So: why not combine vector memory access instructions that convey
>access pattern, with scalar computational operations?

Yes, yes, my point exactly.  Please do it!  I'll take 10.  
In fact, I think a fruitful area for extending the current
architectures is in a more general model for pre-loading
the cache.  Doing pre-loads by constant strides rather
than by contiguous lines would already be a big
performance boost, but I could also imagine more
general solutions, where you gave the memory subsystem a 
vector of addresses which specified the pre-load pattern.

I'm just a user though.  I'm not at all clear how hard these
things would be to implement in hardware.
.