🚀 go-pugleaf

In article <PCG.92Dec23144916@decb.aber.ac.uk>, pcg@aber.ac.uk (Piercarlo Grandi) writes:

|> On a micro level, I am skeptical; there are clearly stretches of code
|> that can be micro parallelized, even vectorized (flow analysis has been
|> vectorized in some Cray compilers, as it is about sweeping boolean
|> matrixes), but overall the processing mustr be sequential. It also
|> depends on the language; for example in C it is conceivable that every
|> function in a source file be compiled in parallel. But this I would
|> regard as macro level parallelism.

We seem to be saying the same things only you keep on talking about macro-level
parallelism as though it would be difficult to exploit, and I feel that the
existence of macro-level parallelism justifies increased superscalarity. It
is my contention that as processors continue to get more and more hyperscalar,
they will be increasingly able to exploit macro-level parallelism without the
help of smart compilers (which will, no doubt continue to improve.) In a
hyperscalar chip it will be necessary to implement tagging and/or scoreboarding
protocols to control resource allocation and make sure that none of the data
gets mixed up. Once this overhead is paid, the protocols can be altered to find
macro level parallelism on their own with very little additional cost in either
performance or area.

Jason W. Solinsky