🚀 go-pugleaf

History repeats itself?  Many early RISC designs chose to expose timing and
pipeline constraints to the software.  It was up to software not to access
data before it arrived, for example.

Successive generations of RISC designs have moved that responsibility back to
hardware.  The original Stanford MIPS had no pipeline interlocks at all - if
the software didn't play by ALL the rules, it got nonsense.  The first
generation of the commercial MIPS architecture cut the constraints down to
two:  You had to wait one extra cyle before trying to use the results of a
load or a multiply, if I remember right.  The second generation of commercial
MIPS has even added hardware interlocks for those.

Delayed branches were a great idea for a while, but recent designs, such as
Alpha, have eschewed them.

The IBM RS/6000 design has NO "correctness" constraints - the RISC-style
optimizations are important for performance, but even without them the program
runs.

Now we are trying the same thing with memory consistency.  Ten years from now,
will we be looking back at those funny experiments of the early '90's that
(a) made the machines such a bitch to program; and (b) didn't really help
beyond a generation or two of design anyway?
							-- Jerry