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Article #10863Re: IBM's FIRST RISC System/6000(tm) based Shared Memory Parallel Processor
From: Phill Hallam-Baker
Date: Sat, 12 Dec 1992 18:05
Date: Sat, 12 Dec 1992 18:05
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2555 bytes
In article <1992Dec11.131542.9190@jarvis.csri.toronto.edu>, hsandhu@sys.toronto.edu (Harjinder S Sandhu) writes: |>chased@rbbb.Eng.Sun.COM (David Chase) writes: |>>I've had this nagging suspicion for about a year that people building |>>MP's were working awfully hard to maintain coherency where it just |>>didn't matter. Given that most of the programming languages tell you |>>to lock your data if it is shared, the "we're guarding against this" |>>examples always looked like buggy programs to me. People have been |>>working on this at Rice, I know, and at least one other place that I |>>cannot recall right now. |> |> Along the same lines, we have implemented and experimented with |>a software coherence strategy based on the notion that applications |>explicitly lock/unlock shared data. It requires no hardware or |>compiler support, but does rely on the programmer to program "correctly". |>This is described in a paper that will be appearing in the 1993 ACM SigPlan |>Symposium on Principles and Practice of Parallel Programming in May: |>"The Shared Regions Approach to Software Cache Coherence on |>Multiprocessors". It will also be made available via ftp soon; send mail |>if you are interested. IBM's approach should be able to streach scalability. hardware cache coherency requires a lot of work. A lot of the time the software does not need the coherency, ergo it makes sense to use software to solve the problem. I disagree with the statement about putting the work onto the programmer though. This work should go into the compiler. this may require a shift away from traditional FORTRAN inspired approaches. The IBM approach would be interesting for CSP. There data is explicitly locked and unlocked. The model also sits very nicely with oops since it *is* a message passing paradigm, -- Phill Hallam-Baker
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Newsgroups: comp.arch Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!dxcern!dscomsa!zeus02.desy.de!hallam From: hallam@zeus02.desy.de (Phill Hallam-Baker) Subject: Re: IBM's FIRST RISC System/6000(tm) based Shared Memory Parallel Processor Message-ID: <Bz5rLE.L9q@dscomsa.desy.de> Keywords: mp shared-memory parallel multiprocessor risc smp Sender: usenet@dscomsa.desy.de (usenet) Reply-To: Hallam@zeus02.desy.de Organization: Deutsches Elektronen Synchrotron, Experiment ZEUS bei HERA References: <Bz0xLu.298v@austin.ibm.com> <1g86boINNh5m@fido.asd.sgi.com> <lifvl6INNan3@exodus.Eng.Sun.COM> <1992Dec11.131542.9190@jarvis.csri.toronto.edu> Date: Sat, 12 Dec 1992 18:05:37 GMT Lines: 37