🚀 go-pugleaf

In article <1g86boINNh5m@fido.asd.sgi.com> mtj@babar.asd.sgi.com (Michael Jones) writes:
> (claim 1) It's been a _long time_ since a multicomputer or other
> non-coherent computing complex was seen as an interesting platform 
> for the problems Mr. Mitchell mentions which include CFD and FEA 
> solvers.

IBM gave a talk on the machine at the cluster workshop. 
It is called the Power/4 now, the Power/128 is in the works. 
Power/4 is 4 cpus, and Power/128 is of course 128. 
Kernel is AIX, but Mach 3.0 runs on it as well. Getting Mach up on the 
machine looked like an adventure, as the MP code assumes coherent caches.
The person who did Mach stated that he felt that much of the work
done would apply to a coherent cache machine as well.
I.e. the things you do to code for a non-coherent cache machine would 
improve performance on a coherent cache machine. My experience agrees
with this.

The speakers stated flatly that coherent cache machines can not scale. 
Here is where you have to watch the use of the word 'scale'. There is 
scalability in that you can add more nodes, a la SCI or KSR; and there is 
performance scalability in that adding more nodes doesn't get you into
N^2 communications  costs (which can easily happen with coherent
cache machines not on a bus; take a look at the time it takes on 
a cache-coherent shared-memory machine using a ring with lots of nodes 
to write a variable which is in every CPUs cache. Examples: MemNet or 
one of its more recent incarnations:see ICPP 91, Computer a month or two ago). 
The Power/128 people are concerned with
performance scalability. [As an aside, the Cray APP, also described at the
workshop, uses a noncoherent cache scheme as well]. 

Currently there are four RS6000s (980s ?), with 128 Mb each, with a crossbar,
and eight shared memory modules. First cut of the crossbar was done
with Xilinx; later cuts are custom. 

In user mode, the shared area obeys the following rules:
1) Granularity of object size for sharing: page size
2) Only ever one writer for a page, multiple readers
3) to sync. a page back, write it to memory and invalidate cached copy

I like the model. I am biased; I started using this model four 
years ago, albeit on an Ethernet. I think they will find a need for some useful
variations on rule (3), however.

ron

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