🚀 go-pugleaf

In article <Bzs3zn.43H.2@cs.cmu.edu> lindsay+@cs.cmu.edu (Donald Lindsay) writes:
>cecchi@rchland.vnet.ibm.com (Del Cecchi) writes:
>>In article <1992Dec22.092355.29859@adobe.com>, zstern@adobe.com (Zalman Stern) writes:
>>|> In particular, is it based on PowerPC or is IBM going to  
>>|> have two 64 bit RISC architectures floating around.
>
>>"IBM doesn't comment on un-announced machines"
>
>The workstation group has tried to persuade the rest of IBM to use
>its silicon. As long as the division making the AS/400 is profitable,
>it will have the option of resisting this pressure.

The AS/400 uses a tagged memory-system and tagged registers to protect
capabilities (or pointers, as they call them).  There are also a number of
operations that only take place on capabilities.  This makes it rather unlikely
that they'd use a stock micro-processor from the workstation group.  You could, 
of course, either emulate these features in software, or modify the basic
PowerPC architecture.  The first, however would be very inefficient (you'd have
to check every memory reference to see if you're working with a capability or a
data item), and the second *could* involve extensive modifications to the basic
PowerPC architecture and implementations.

I'd bet IBM will have two 64-bit architectures floating around.  Besides, I've
heard rumors that the pointers on this improved AS/400 are going to be extended
to 96-bits, anyway. That would probably rule out PowerPC right away.

-- 
    				|   Eric Koldinger
    Your tax dollars at play.	|   University of Washington
	 			|   Department of Computer Science
				|   kolding@cs.washington.edu