🚀 go-pugleaf

In article <1992Dec14.072942.21962@doug.cae.wisc.edu>
	keiths@cae.wisc.edu (Keith Scidmore) writes:

>1)  I read that the 21064 divide unit is not pipelined and takes one cycle 
>    per bit to produce a result.  Isn't this going to kill floating point
>    performance? [...] I'm
>    lead to think that DEC isn't interested in the FP performance of this chip,
>    or do I have my facts wrong?

A double precision floating point divide is slow, but look at the benchmark
results: the Alpha AXP 10000 is rated at 200 SPECfp92.  If you buy the
low-end model you get 112 SPECfp92.  Obviously divide performance isn't
critical to this large selection of real-world applications.

In any case, considering the clock speed difference between Alpha AXP and
competitive systems you are better off counting nanoseconds instead of
cycles:

			DEC Alpha AXP			IBM RS 6000
			 	133 Mhz	150 Mhz		 	41 Mhz	62.5 Mhz
			cycles	ns	ns		cycles	ns	ns
FP mult or add		 6	 45	 40		 2	 48	 32
FP divide		63	473	420		20	480	320

This shows floating point latency of the low/mid range Alpha systems to be
similar to the IBM RS/6000.  But this is the worst-case* performance.  The
Alpha can execute 6 independent floating point operations in parallel, and
most floating point code can use at least part of this parallelism.


*Both Alpha and RS/6000 are slower when handling infinities, NaNs, or
denormals, but for most applications this is not an important consideration.


>3)  The manuals say that the 21064 is superpipelined.  Where?  How can this
>    claim be justified in light of the floating point divider not being
>    pipelined at all?

I first heard the term "superpipelined" applied to the MIPS R4000, which
does not pipeline integer multiply or divide (I don't know if it pipelines
floating point divide).


	John Carr
	jfc@grouse.dsg.dec.com

	All facts and opinions in this article are the responsibility
	of the author, not DEC.