🚀 go-pugleaf

chased@rbbb.Eng.Sun.COM (David Chase) writes:
> We describe an efficient software cache consistency mechanism for shared
> memory multiprocessors that supports multiple writers and works for
> cache lines of any size.  Our mechanism relies on the fact that, for a
> correct program, only the global memory needs a consistent view of the
> shared data between synchronization points.  Our delayed consistency
> mechanism allows arbitrary use of data blocks between synchronizations.

cliffc@rice.edu (Cliff Click) writes:
>This sounds like an paraphrase of Ervan Darnell's thesis proposal here
>at Rice.  IBM funds a lot of Rice research, so this might be where IBM
>is coming from.  Send replies to ervan@cs.rice.edu.  Of course, I've
>been wrong before (and I haven't checked with Ervan on this).

This idea is quite old. It was the subject of a tech report six years ago:

%A D. Abramson
%A K. Ramamohanarao
%A M. Ross
%T A software controlled cache coherence policy,
using selectively clearable cache memories
%R Technical Report 86/18
%I Department of Computer Science, University of Melbourne
%C Melbourne, Australia
%D 1986

The paper was difficult to publish, as it seems to have been ahead of its time.
It finally appeared as

%A D. Abramson
%A K. Ramamohanarao
%A M. Ross
%T A scalable cache coherence mechanism
using a selectively clearable cache memory
%J Australian Computer Journal
%K acj
%V 21
%N 1
%D February 1989
%P 2-12

Zoltan Somogyi <zs@cs.mu.OZ.AU>
Department of Computer Science, University of Melbourne, AUSTRALIA