Re: User visible pipelines vs. user visible memory coherency.

Article View: comp.arch

Article #10954

#10954

From: peter da silva
Date: Tue, 15 Dec 1992 02:54

13 lines
1135 bytes

[DEC dumping branch delay slots]

In article <1992Dec14.030757.14209@adobe.com> zstern@adobe.com (Zalman Stern) writes:
> Without any real compelling arguments that I've heard.

I think the theory is that if they're going to have a bunch of instruction
prefetching anyway, it's not a win, and they expect more rather than less
instruction reordering in silicon in the future.
-- 
%Peter da Silva/77487-5012 USA/+1 713 274 5180/Have you hugged your wolf today?
/L{lineto}def/C{curveto}def/F{0 562 moveto 180 576 324 648 396 736 C 432 736 L
482 670 518 634 612 612 C}def/G{setgray}def .75 G F 612 792 L 0 792 L fill 1 G
324 720 24 0 360 arc fill 0 G 3 setlinewidth F stroke showpage % "Peerless"

Technical Details

Message-ID: <id.GGUV.TQJ@ferranti.com>

Path: arc1-ca.pugleaf.net!sparky!uunet!zaphod.mps.ohio-state.edu!menudo.uh.edu!sugar!ficc!peter

References: <1992Dec12.102403.1@zodiac.rutgers.edu> <1992Dec14.030757.14209@adobe.com>

Show Full Headers

Complete Article Headers

Newsgroups: comp.arch
Path: arc1-ca.pugleaf.net!sparky!uunet!zaphod.mps.ohio-state.edu!menudo.uh.edu!sugar!ficc!peter
From: peter@ferranti.com (peter da silva)
Subject: Re: User visible pipelines vs. user visible memory coherency.
Message-ID: <id.GGUV.TQJ@ferranti.com>
Organization: Xenix Support, FICC
References: <1992Dec12.102403.1@zodiac.rutgers.edu> <1992Dec14.030757.14209@adobe.com>
Date: Tue, 15 Dec 1992 02:54:00 GMT
Lines: 13

Reply to Parent Message