0 Wait states and caches

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Article #10988

#10988

From: Andrea Gozzi
Date: Fri, 25 Dec 1992 18:39

20 lines
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I'm almost a novice in comp.arch, but i have a question for the net.
Today i received a 486SX motherboard at 25MHz. 
It is possible to install an external SRAM cache, but it is not currently
installed on board.
Well, i experimented with the setup for a while and discovered that the board
works at 25MHz with 0 wait states without SRAM cache.

What is the difference in operating at 0wait states with or without
cahce? Installing the cache would make any difference ?

By logic, i'd say no, but if not, for which kind of reason 
did they included the cache possibility?

Andrea
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Path: arc1-ca.pugleaf.net!sparky!uunet!spool.mu.edu!agate!stanford.edu!rutgers!modus!gear!forum!work
From: work@forum.sublink.org (Andrea Gozzi)
Newsgroups: comp.arch
Subject: 0 Wait states and caches
Message-ID: <670@forum.sublink.org>
Date: 25 Dec 92 18:39:43 GMT
Organization: Forum Graphics Exchange in Correggio (RE) ITALY
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