Article View: comp.arch
Article #11023Re: Lisp performance (on Sparc SS2, SS10-30, HP720)
From: Jay Lessert
Date: Mon, 16 Nov 1992 18:57
Date: Mon, 16 Nov 1992 18:57
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1173 bytes
In article <Bxt992.BJB@pix.com> stripes@pix.com (Josh Osborne) writes:
>In article <1e824rINNlpu@iraul1.ira.uka.de> wolpers@i11s10.ira.uka.de (Andreas Wolpers) writes:
>>I can buy enough memory so that disk speed is no criterion.
>>Should I wait for machines with 8MB of cache? Should I shoot myself?
>
>How long can you wait? Wait long enough and lisp machines will come
>back into style (half :-) ).
Hey, the Solbourne Series6 (Viking) CPU boards have 16MB of static third
level cache, no waiting necessary! :-)
--
Jay Lessert {decwrl,cse.ogi.edu,sun,verdix}!bit!jayl
Bipolar Integrated Technology, Inc.
503-629-5490 (fax)503-690-1498
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arc1-ca.pugleaf.net!sparky!uunet!charon.amdahl.com!pacbell.com!ames!saimiri.primate.wisc.edu!caen!sol.ctr.columbia.edu!emory!ogicse!verdix!bit!jaylReferences:
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Path: arc1-ca.pugleaf.net!sparky!uunet!charon.amdahl.com!pacbell.com!ames!saimiri.primate.wisc.edu!caen!sol.ctr.columbia.edu!emory!ogicse!verdix!bit!jayl From: jayl@bit.UUCP (Jay Lessert) Newsgroups: comp.arch,comp.benchmarks Subject: Re: Lisp performance (on Sparc SS2, SS10-30, HP720) Message-ID: <489@bit.UUCP> Date: 16 Nov 92 18:57:04 GMT Article-I.D.: bit.489 References: <1e824rINNlpu@iraul1.ira.uka.de> <Bxt992.BJB@pix.com> Reply-To: jayl@bit.UUCP (Jay Lessert) Organization: BIT Inc., Portland, OR USA Lines: 15